參數(shù)資料
型號: AD9558BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 66/104頁
文件大?。?/td> 0K
描述: IC CLK XLATR PLL 1250MHZ 64LFCSP
產品變化通告: AD9558 Minor Metal Mask Change 17/Apr/2012
標準包裝: 750
類型: 時鐘/頻率轉換器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,HSTL,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 4:6
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.25GHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
AD9558
Data Sheet
Rev. B | Page 64 of 104
Reg
Addr
(Hex)
Opt
Name
D7
D6
D5
D4
D3
D2
D1
D0
Def
0x0323
L
Base loop
Filter A
coefficient set
(normal phase
margin of 70)
NPM Alpha-0[7:0]
24
0x0324
L
NPM Alpha-0[15:8]
8C
0x0325
L
Reserved
NPM Alpha-1[6:0]
49
0x0326
L
NPM Beta-0[7:0]
55
0x0327
L
NPM Beta-0[15:8]
C9
0x0328
L
Reserved
NPM Beta-1[6:0]
7B
0x0329
L
NPM Gamma-0[7:0]
9C
0x032A
L
NPM Gamma-0[15:8]
FA
0x032B
L
Reserved
NPM Gamma-1[6:0]
55
0x032C
L
NPM Delta-0[7:0]
EA
0x032D
L
NPM Delta-0[15:8]
E2
0x032E
L
Reserved
NPM Delta-1[6:0]
57
Output PLL (APLL)
0x0400
APLL charge
pump
Output PLL (APLL) charge pump[7:0]
81
0x0401
APLL N divider
Output PLL (APLL) feedback N divider[7:0]
14
0x0402
Reserved
00
0x0403
APLL loop
filter control
APLL loop filter control[7:0]
07
0x0404
Reserved
Bypass
internal Rzero
00
0x0405
APLL VCO
control
Reserved (default: 0x2)
APLL locked
controlled
sync disable
Reserved
Manual APLL
VCO (not
autoclearing)
20
0x0406
Reserved
00
0x0407
RF divider
RF Divider 2[3:0]
RF Divider 1[3:0]
44
0x0408
Reserved
RF divider
startup
mode
Reserved
PD RF Divider 2
PD RF Divider 1
02
Output Clock Distribution
0x0500
Distribution
output sync
Mask
Channel 3
sync
Mask
Channel 2
sync
Mask
Channel 1
sync
Mask
Channel 0
sync
Reserved
Sync
source
selection
Automatic sync mode
02
0x0501
Channel 0
Enable 3.3 V
CMOS driver
OUT0 format[2:0]
OUT0 polarity[1:0]
OUT0 drive
strength
Enable OUT0
10
0x0502
Channel 0 (M0) division ratio[7:0]
00
0x0503
Reserved
Channel 0 PD
Select RF
Divider 2
Channel 0 (M0) division ratio[9:8]
00
0x0504
Reserved
Channel 0 divider phase[5:0]
00
0x0505
Channel 1
Reserved
OUT1 format[2:0]
OUT1 polarity[1:0]
OUT1 drive
strength
Enable OUT1
10
0x0506
Reserved
OUT2 format[2:0]
OUT2 polarity[1:0]
OUT2 drive
strength
Enable OUT2
10
0x0507
Channel 1 (M1) division ratio[7:0]
03
0x0508
Reserved
Channel 1 PD
Select RF
Divider 2
Channel 1 (M1) division ratio[9:8]
00
0x0509
Reserved
Channel 1 divider phase[5:0]
00
0x050A
Channel 2
Reserved
OUT3 format[2:0]
OUT3 polarity[1:0]
OUT3 drive
strength
Enable OUT3
10
0x050B
Reserved
OUT4 format[2:0]
OUT4 polarity[1:0]
OUT4 drive
strength
Enable OUT4
10
0x050C
Channel 2 (M2) division ratio[7:0]
00
0x050D
Reserved
Channel 2 PD
Select RF
Divider 2
Channel 2 (M2) division ratio[9:8]
00
0x050E
Reserved
Channel 2 divider phase[5:0]
00
0x050F
Channel 3
Enable 3.3 V
CMOS driver
OUT5 format[2:0]
OUT5 polarity[1:0]
OUT5 drive
strength
Enable OUT5
10
0x0510
Channel 3, Divider 1 (M3) division ratio[7:0]
03
0x0511
Reserved
Channel 3, Divider 1 (M3)
division ratio[9:8]
00
0x0512
Channel 3, Divider 2 (M3b) division ratio[7:0]
00
0x0513
Reserved
Enable
Channel 3
doubler
Channnel 3
PD
Select RF
Divider 2
Channel 3, Divider 2 (M3b)
division ratio[9:8]
00
0x0514
Reserved
Channel 3, Divider 1 phase[5:0]
00
0x0515
Reserved
Channel 3, Divider 2 phase[5:0]
00
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