參數(shù)資料
型號: AD9520-5BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 71/76頁
文件大?。?/td> 0K
描述: IC CLOCK GEN EXT VCO 64LFCSP
設(shè)計資源: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標準包裝: 750
類型: 時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:12,2:24
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
Data Sheet
AD9520-5
Rev. A | Page 73 of 76
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9520 do not supply enough current
to provide a full voltage swing with a low impedance resistive, far-
end termination, as shown in Figure 63. The far-end termination
network should match the PCB trace impedance and provide the
desired switching point. The reduced signal swing may still meet
receiver input requirements in some applications. This can be
useful when driving long trace lengths on less critical nets.
Figure 63. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9520 offers LVPECL outputs
that are better suited for driving long traces where the inherent
noise immunity of differential signaling provides superior
performance for clocking converters.
CMOS
10
50
100
VS
07239-
077
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