參數(shù)資料
型號： AD9520-5BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 33/76頁
文件大小： 0K
描述： IC CLOCK GEN EXT VCO 64LFCSP
設(shè)計資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
Data Sheet
AD9520-5
Rev. A | Page 39 of 76
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the CLK to the output is
the product of the VCO divider (1, 2, 3, 4, 5, and 6) and the
division of the channel divider. Table 28 shows how the frequency
division for a channel is set.
Table 28. Frequency Division
VCO Divider
Setting1
Channel
Divider
Setting
CLK Direct-
to-Output
Setting
Resulting
Frequency
Division
1 to 6
Don’t care
Enable
1
1 to 6
2 to 32
Disable
(1 to 6) × (2 to 32)
2 to 6
Bypass
Disable
(2 to 6) × (1)
1
Bypass
Disable
Output static
(illegal state)
VCO divider
bypassed
Bypass
Don’t care
1
VCO divider
bypassed
2 to 32
Don’t care
2 to 32
1
The bypass VCO divider (Register 0x1E1[0] = 1b) is not the same as VCO
divider = 1 (divide-by-1).
The channel dividers feeding the output drivers contain one
2-to-32 frequency divider. This divider provides for division-by-1
to division-by-32. Division-by-1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal of
up to 1600 MHz at their inputs across all channel divider ratios.
The features and settings of the dividers are selected by program-
ming the appropriate setup and control registers (see Table 44
VCO Divider
The VCO divider provides frequency division between the CLK
input and the clock distribution channel dividers. The VCO
divider can be set to divide by 1, 2, 3, 4, 5, or 6 (see Table 51,
Register 0x1E0[2:0]). However, when the VCO divider is set to 1,
none of the channel output dividers can be bypassed.
The VCO divider can also be set to static, which is useful for
applications where the only desired output frequency is the
CLK input frequency. Making the VCO divider static increases
the wide band spurious-free dynamic range (SFDR).
Channel Dividers
A channel divider drives each group of three LVPECL outputs.
There are four channel dividers (0, 1, 2, and 3) driving 12 LVPECL
outputs (OUT0 to OUT11). Table 29 lists the bit locations used
for setting the division and other functions of these dividers. The
division is set by the M and N values. The divider can be bypassed
(equivalent to divide-by-1, divider circuit is powered down) by
setting the bypass bit.
The duty-cycle correction can be enabled or disabled according
to the setting of the disable Divider x DCC bits.
Table 29. Setting DX for the Output Dividers
Divider
Low Cycles,
MValue Bits
High Cycles,
N Value Bits
Bypass
Bits
Disable
Divider x
DCC Bits
0
0x190[7:4]
0x190[3:0]
0x191[7]
0x192[0]
1
0x193[7:4]
0x193[3:0]
0x194[7]
0x195[0]
2
0x196[7:4]
0x196[3:0]
0x197[7]
0x198[0]
3
0x199[7:4]
0x199[3:0]
0x19A[7]
0x19B[0]
Channel Divider Maximum Frequency
The maximum frequency at which all features of the channel
divider are guaranteed to work is 1.6 GHz; this is the number
that appears elsewhere in the datasheet. The maximum frequency
at which all features of the channel divider are guaranteed to work
is 1.6 GHz; this is the number that appears elsewhere in the data
sheet. However, if the divide-by-3 and divide-by-17 settings are
avoided, the maximum channel divider input frequency is 2 GHz.
Channel Frequency Division (0, 1, 2, or 3)
For each channel (where the channel number (x) is 0, 1, 2, or 3),
the frequency division, DX, is set by the values of M and N
(four bits each, representing Decimal 0 to Decimal 15), where
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
The high and low cycles are the cycles of the clock signal that
are currently routed to the input of the channel dividers (VCO
divider out or CLK).
When a divider is bypassed, DX = 1.
Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows
each channel divider to divide by any integer from 2 to 32.
Duty Cycle and Duty-Cycle Correction
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
M and N values for the channel
DCC enabled/disabled
VCO divider enabled/bypassed
CLK input duty cycle
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the disable Divider x DCC bit
for that channel.
Certain M and N values for a channel divider result in a non-
50% duty cycle. A non-50% duty cycle can also result in an
even division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle.
相關(guān)PDF資料
PDF描述
AD9522-0BCPZ-REEL7 IC CLOCK GEN 2.8GHZ VCO 64LFCSP
AD9522-1BCPZ-REEL7 IC CLOCK GEN 2.5GHZ VCO 64LFCSP
AD9522-2BCPZ IC CLOCK GEN 2.2GHZ VCO 64LFCSP
AD9522-3BCPZ-REEL7 IC CLOCK GEN 2GHZ VCO 64LFCSP
AD9522-4BCPZ-REEL7 IC CLOCK GEN 1.6GHZ VCO 64LFCSP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9521JH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521KH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521SE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521SH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521TE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*