參數(shù)資料
型號： AD9520-5BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 28/76頁
文件大?。?/td> 0K
描述： IC CLOCK GEN EXT VCO 64LFCSP
設(shè)計資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標準包裝： 750
類型： 時鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9520-5
Data Sheet
Rev. A | Page 34 of 76
The analog lock detect function requires an RC filter to provide a
logic level indicating lock/unlock. The ADIsimCLK tool can be
used to help the user select the right passive component values
for ALD to ensure its correct operation.
Figure 32. Example of Analog Lock Detect Filter Using
N-Channel Open-Drain Driver
Current Source Digital Lock Detect (CSDLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is possible by using the
current source digital lock detect function.
Figure 33. Current Source Digital Lock Detect
The current source lock detect provides a current of 110 A when
DLD is true and shorts to ground when DLD is false. If a capacitor
is connected to the LD pin, it charges at a rate determined by the
current source during the DLD true time but is discharged nearly
instantly when DLD is false. By monitoring the voltage at the
LD pin (top of the capacitor), LD = high happens only after the
DLD is true for a sufficiently long time. Any momentary DLD
false resets the charging. By selecting a properly sized capacitor,
it is possible to delay a lock detect indication until the PLL is
stably locked and the lock detect does not chatter.
To use current source digital lock detect, do the following:
Place a capacitor to ground on the LD pin.
Set Register 0x01A[5:0] = 0x04.
Enable the LD pin comparator (Register 0x01D[3] = 1b).
The LD pin comparator senses the voltage on the LD pin, and
the comparator output can be made available at the REFMON
pin control (Register 0x01B[4:0]) or the STATUS pin control
(Register 0x017[7:2]). The internal LD pin comparator trip point
and hysteresis are given in Table 14. The voltage on the capacitor
can also be sensed by an external comparator that is connected
to the LD pin. In this case, enabling the on-board LD pin
comparator is not necessary.
The user can asynchronously enable individual clock outputs only
when CSDLD is high. To enable this feature, set the appropriate bits
in the enable output on the CSDLD registers (Register 0x0FC and
Register 0x0FD).
External VCXO/VCO Clock Input (CLK/CLK)
This differential input is used to drive the AD9520 clock
distribution section. This input can receive up to 2.4 GHz.
The pins are internally self-biased, and the input signal should
be ac-coupled via capacitors.
Figure 34. CLK Equivalent Input Circuit
The CLK/CLK input can be used either as a distribution only
input (with the PLL off) or as a feedback input for an external
VCO/VCXO using the internal PLL.
Holdover Mode
The AD9520 PLL has a holdover function. Holdover mode allows
the external VCO to maintain a relatively constant frequency
even though there is no reference clock. This function is useful
when the PLL reference clock is lost. Holdover is implemented
by placing the charge pump in a high impedance state. Without
this function, the charge pump is placed into a constant pump-up
or pump-down state, resulting in a massive VCO frequency shift.
Because the charge pump is placed in a high impedance state,
any leakage that occurs at the charge pump output or the VCO
tuning node causes a drift of the VCO frequency. This drift can
be mitigated by using a loop filter that contains a large capacitive
component because this drift is limited by the current leakage
induced slew rate (ILEAK/C) of the VCO control voltage.
Both a manual holdover mode, using the SYNC pin, and an
automatic holdover mode are provided. To use either function, the
holdover function must be enabled (Register 0x01D[0]).
Manual/External Holdover Mode
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when
the SYNC pin is asserted low. This operation is edge sensitive,
not level sensitive. The charge pump enters a high impedance
state immediately. To take the charge pump out of a high
impedance state, take the SYNC pin high. The charge pump
then leaves the high impedance state synchronously with the next
PFD rising edge from the reference clock. This prevents
extraneous charge pump events from occurring during the time
between SYNC going high and the next PFD event. This also
AD9520
ALD
LD
R1
C
VOUT
R2
VS = 3.3V
07239-
067
AD9520
LD
REFMON
OR
STATUS
C
VOUT
110A
DLD
LD PIN
COMPARATOR
07239-
068
VS
CLOCK INPUT
STAGE
CLK
5k
2.5k
07239-
032
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