參數(shù)資料
型號(hào)： AD7856ARS
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC
中文描述： 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封裝： SHRINK, SOP-24
文件頁數(shù)： 4/32頁
文件大?。?/td> 294K
代理商： AD7856ARS
AD7856
TIMING SPECIFICATIONS
1
(V
DD
= 5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. A Grade: f
CLKIN
= 6 MHz; K Grade: f
CLKIN
= 4 MHz.)
–4–
REV. A
Limit at T
MIN
, T
MAX
A Version
Parameter
f
CLKIN2
K Version
Units
Description
500
6
6
100
50
3.5
–0.4 t
SCLK
±
0.4 t
SCLK
30
30
45
30
20
0.4 t
SCLK
0.4 t
SCLK
30
30/0.4 t
SCLK
50
90
50
2.5 t
CLKIN
2.5 t
CLKIN
41.7
500
4
4
100
50
5.25
–0.4 t
SCLK
±
0.4 t
SCLK
50
50
75
40
20
0.4 t
SCLK
0.4 t
SCLK
30
30/0.4 t
SCLK
50
90
50
2.5 t
CLKIN
2.5 t
CLKIN
62.5
kHz min
MHz max
MHz max
ns min
ns max
μ
s max
ns min
ns min/max
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ms typ
Master Clock Frequency
f
SCLK
t
13
t
2
t
CONVERT
t
3
CONVST
Pulsewidth
CONVST
↓
to BUSY
↑
Propagation Delay
Conversion Time = 20 t
CLKIN
SYNC
↓
to SCLK
↓
Setup Time (Noncontinuous SCLK Input)
SYNC
↓
to SCLK
↓
Setup Time (Continuous SCLK Input)
Delay from
SYNC
↓
Until DOUT 3-State Disabled
Delay from
SYNC
↓
Until DIN 3-State Disabled
Data Access Time After SCLK
↓
Data Setup Time Prior to SCLK
↑
Data Valid to SCLK Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK
↑
to
SYNC
↑
Hold Time (Noncontinuous SCLK)
(Continuous SCLK)
Delay from
SYNC
↑
Until DOUT 3-State Enabled
Delay from
SCLK
↑
to DIN Being Configured as Output
Delay from
SCLK
↑
to DIN Being Configured as Input
CAL
↑
to BUSY
↑
Delay
CONVST
↓
to BUSY
↑
Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(250026 t
CLKIN
)
Internal DAC Plus System Full-Scale Cal Time, Master
Clock Dependent (222228 t
CLKIN
)
System Offset Calibration Time, Master Clock Dependent
(27798 t
CLKIN
)
t
44
t
54
t
64
t
7
t
8
t
9
t
10
t
11
t
125
t
t
13
t
15
t
16
t
CAL
t
CAL1
37.04
55.5
ms typ
t
CAL2
4.63
6.94
ms typ
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
See Table X and timing diagrams for different interface modes and calibration.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The
CONVST
pulsewidth here only applies for normal operation. When the part is in power-down mode, a different
CONVST
pulsewidth will apply
(see Power-Down section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
6
t
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
, quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
Specifications subject to change without notice.
相關(guān)PDF資料
PDF描述
AD7856KR 5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC
AD7856 8-Channel 14 Bit 285 kSPS Sampling ADC(單電源,8通道14位采樣A/D轉(zhuǎn)換器)
AD7858L 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC(單電源,200kSPS 8通道12位采樣A/D轉(zhuǎn)換器)
AD7858 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC(單電源,200kSPS 8通道12位采樣A/D轉(zhuǎn)換器)
AD7859AP 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7856ARS-REEL 制造商:Analog Devices 功能描述:ADC Single SAR 285ksps 14-bit Serial 24-Pin SSOP T/R
AD7856ARS-REEL7 制造商:Analog Devices 功能描述:ADC Single SAR 285ksps 14-bit Serial 24-Pin SSOP T/R
AD7856ARSZ 功能描述:IC ADC 14BIT 8CHAN 5V 24SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
AD7856ARSZ-REEL7 功能描述:IC ADC 14BIT 8CHAN 5V 24SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
AD7856ARZ 功能描述:IC ADC 14BIT 8CHAN 5V 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
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