參數(shù)資料
型號(hào): AD7856ARS
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC
中文描述: 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封裝: SHRINK, SOP-24
文件頁(yè)數(shù): 26/32頁(yè)
文件大小: 294K
代理商: AD7856ARS
AD7856
–26–
REV. A
CONFIGURING THE AD7856
The AD7856 contains 14 on-chip registers that can be accessed
via the serial interface. In the majority of applications it will not
be necessary to access all of these registers. Here the CLKIN
signal is applied directly after power-on, the CLKIN signal must
be present to allow the part to perform a calibration. This auto-
matic calibration will be completed approximately 150 ms
after power-on.
Writing to the AD7856
For accessing the on-chip registers it is necessary to write to the
part. To change the channel from the default channel setting the
user will be required to write to the part. To enable Serial Inter-
face Mode 1 the user must also write to the part. Figures 34 and
35 outline flowcharts of how to configure the AD7856 Serial
Interface Modes 1 and 2 respectively. The continuous loops on
all diagrams indicate the sequence for more than one conversion.
START
POWER-ON, APPLY CLKIN SIGNAL,
WAIT 150ms FOR AUTOMATIC CALIBRATION
APPLY
SYNC
(IF REQUIRED), SCLK,
WRITE TO CONTROL REGISTER
SETTING CHANNEL AND TWO-WIRE MODE
PULSE
CONVST
PIN
WAIT FOR BUSY SIGNAL TO GO LOW
OR
WAIT FOR BUSY BIT = 0
1
SERIAL
INTERFACE
MODE
READ
DATA
DURING
CONVERSION
NO
YES
APPLY
SYNC
(IF REQUIRED), SCLK, READ
CURRENT CONVERSION RESULT ON DIN PIN
APPLY
SYNC
(IF REQUIRED), SCLK, READ
PREVIOUS CONVERSION RESULT ON DIN PIN
WAIT APPROX. 200 ns AFTER
CONVST
RISING EDGE OR AFTER END
OF CONTROL REGISTER WRITE
Figure 34. Flowchart for Setting Up, Reading and Writing in Interface Mode 1
The options of using a hardware (pulsing the
CONVST
pin) or
software (setting the CONVST bit to 1) conversion start, and
reading/writing during or after conversion are shown in Figures
34 and 35. If the
CONVST
pin is never used, it should be
permanently tied to DV
DD
. Where reference is made to the
BUSY bit equal to a Logic 0, to indicate the end of conversion,
the user in this case would poll the BUSY bit in the status register.
Interface Mode 1 Configuration
Figure 34 shows the flowchart for configuring the part in Inter-
face Mode 1. This mode of operation can only be enabled by
writing to the control register and setting the 2/
3
MODE bit.
Reading and writing cannot take place simultaneously in this
mode as the DIN pin is used for both reading and writing.
Initiating conversions in software is not recommended in this
mode, see Detailed Timing section.
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