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參數(shù)資料
| 型號： | AD73360LARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONTEND 6CH 28SOIC |
| 標準包裝： | 400 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 6 |
| 功率（瓦特）： | 80mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
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REV. A
AD73360
–9–
PIN FUNCTION DESCRIPTION
Mnemonic
Function
VINP1
Analog Input to the Positive Terminal of Input Channel 1.
VINN1
Analog Input to the Negative Terminal of Input Channel 1.
VINP2
Analog Input to the Positive Terminal of Input Channel 2.
VINN2
Analog Input to the Negative Terminal of Input Channel 2.
VINP3
Analog Input to the Positive Terminal of Input Channel 3.
VINN3
Analog Input to the Negative Terminal of Input Channel 3.
VINP4
Analog Input to the Positive Terminal of Input Channel 4.
VINN4
Analog Input to the Negative Terminal of Input Channel 4.
VINP5
Analog Input to the Positive Terminal of Input Channel 5.
VINN5
Analog Input to the Negative Terminal of Input Channel 5.
VINP6
Analog Input to the Positive Terminal of Input Channel 6.
VINN6
Analog Input to the Negative Terminal of Input Channel 6.
REFOUT
Buffered Reference Output, which has a nominal value of 1.25 V or 2.5 V, the value being dependent on the status
of Bit 5VEN (CRC:7).
REFCAP
A Bypass Capacitor to AGND2 of 0.1
F is required for the on-chip reference. The capacitor should be fixed to
this pin. This pin can be overdriven by an external reference if required.
AVDD2
Analog Power Supply Connection.
AGND2
Analog Ground/Substrate Connection.
DGND
Digital Ground/Substrate Connection.
DVDD
Digital Power Supply Connection.
RESET
Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital
circuitry.
SCLK
Output Serial Clock whose rate determines the serial transfer rate to/from the AD73360. It is used to clock data or
control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the
master clock (MCLK) divided by an integer number—this integer number being the product of the external mas-
ter clock rate divider and the serial clock rate divider.
MCLK
Master Clock Input. MCLK is driven from an external clock signal.
SDO
Serial Data Output of the AD73360. Both data and control information may be output on this pin and are clocked
on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is
low.
SDOFS
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period
before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in
three-state when SE is low.
SDIFS
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one SCLK period
before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored
when SE is low.
SDI
Serial Data Input of the AD73360. Both data and control information may be input on this pin and are clocked on
the negative edge of SCLK. SDI is ignored when SE is low.
SE
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease
power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original values
(before SE was brought low); however, the timing counters and other internal registers are at their reset values.
AGND1
Analog Ground Connection.
AVDD1
Analog Power Supply Connection.
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