參數(shù)資料
型號： AD73360LARZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 17/35頁
文件大?。?/td> 0K
描述： IC PROCESSOR FRONTEND 6CH 28SOIC
標(biāo)準(zhǔn)包裝： 400
位數(shù)： 16
通道數(shù)： 6
功率（瓦特）： 80mW
電壓 - 電源，模擬： 3V
電壓 - 電源，數(shù)字： 3V
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
REV. A
AD73360
–24–
1/2
74HC74
CLK
DQ
DSP CONTROL
TO SE
MCLK
SE SIGNAL SYNCHRONIZED
TO MCLK
1/2
74HC74
CLK
DQ
DSP CONTROL
TO
RESET
MCLK
RESET SIGNAL SYNCHRONIZED
TO MCLK
Figure 19. SE and
RESET Sync Circuit for Cascaded
Operation
PERFORMANCE
As the AD73360 is designed to provide high performance, low
cost conversion, it is important to understand the means by
which this high performance can be achieved in a typical appli-
cation. This section will, by means of spectral graphs, outline
the typical performance of the device and highlight some of the
options available to users in achieving their desired sample rate,
either directly in the device or by doing some post-processing in
the DSP, while also showing the advantages and disadvantages
of the different approaches.
Encoder Section
The encoder section samples at DMCLK/256, which gives a
64 kHz output rate for DMCLK equal to 16.384 MHz. The
noise-shaping of the sigma-delta modulator also depends on the
frequency at which it is clocked, which means that the best
dynamic performance in a particular bandwidth is achieved by
oversampling at the highest possible rate. If we assume that the
signals of interest are in the voice bandwidth of dc–4 kHz, then
sampling at 64 kHz gives a spectral response which ensures
good SNR performance in the voice bandwidth, as shown in
Figure 20.
FREQUENCY – kHz
0
dBs
–20
816
24
32
–100
–140
–120
–40
–60
–80
SNR = 59.0dB (DC TO fS/2)
SNR = 80.8dB (DC TO 4kHz)
Figure 20. FFT (ADC 64 kHz Sampling)
The sampling rate can be varied by programming the Decimation
Rate Divider settings in CRB. For a DMCLK of 16.384 MHz
sample rates of 64 kHz, 32 kHz, 16 kHz and 8 kHz are available.
Figure 21 shows the final spectral response of a signal sampled
at 8 kHz using the maximum oversampling rate.
FREQUENCY – kHz
0
dBs
–20
24
–100
–140
–120
–40
–60
–80
SNR = 80dBs (DC TO 4kHz)
Figure 21. FFT (ADC 8 kHz Internally Decimated from
64 kHz)
It is possible to generate lower sample rates through reducing
the oversampling ratio by programming the DMCLK Rate
Divider Settings in CRB (MCD2-MCD1) This will have the
effect of spreading the quantization noise over a lesser band-
width resulting in a degradation of dynamic performance.
Figure 22 shows a FFT plot of a signal sampled at 8 kHz rate
produced by reducing the DMCLK Rate.
FREQUENCY – kHz
0
dBs
–20
24
–100
–140
–120
–40
–60
–80
SNR = 72.2dBs (DC TO fS/2)
Figure 22. FFT (ADC 8 kHz Sampling with Reduced
DMCLK Rate)
相關(guān)PDF資料
PDF描述
MAX965EUA+ IC COMPARATOR R-R 8-UMAX
MAX966ESA+ IC COMPARATOR R-R 8-SOIC
VE-JN4-MY-F1 CONVERTER MOD DC/DC 48V 50W
MAX965ESA+ IC COMPARATOR R-R 8-SOIC
VE-JN3-MY-F4 CONVERTER MOD DC/DC 24V 50W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7339 制造商:AD 制造商全稱:Analog Devices 功能描述:5 V Integrated High Speed ADC/Quad DAC System
AD7339BS 制造商:Analog Devices 功能描述:Data Acquisition System Single ADC Quad DAC 8-Bit 52-Pin MQFP
AD7339BS-REEL 制造商:Analog Devices 功能描述:Data Acquisition System Single ADC Quad DAC 8-Bit 52-Pin MQFP T/R
AD7339BSZ-REEL 功能描述:IC ADC/QUAD DAC 5V W/REF 52-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤
AD734 制造商:AD 制造商全稱:Analog Devices 功能描述:10 MHz, 4-Quadrant Multiplier/Divider
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*