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參數(shù)資料
| 型號： | AD73360LARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/35頁 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR FRONTEND 6CH 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 6 |
| 功率（瓦特）： | 80mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
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REV. A
AD73360
–25–
Figure 23 shows a comparison of SNR results achieved by vary-
ing either the Decimation Rate Setting or the DMCLK Rate
Settings.
SAMPLING FREQUENCY – kHz
8
SNR
–
dBs
71
REDUCED
DMCLK
DMCLK = MCLK
72
73
74
75
76
77
78
79
80
81
16
24
32
40
48
56
64
Figure 23. Comparison of DMCLK and Decimation Rate
Settings
Encoder Group Delay
The AD73360 implementation offers a very low level of group
delay, which is given by the following relationship:
Group Delay (Decimator) = Order
× ((M–1)/2) × Tdec
where:
Order is the order of the decimator (= 3),
M is the decimation factor (= 32) and
Tdec is the decimation sample interval (= 1/2.048e6)
=> Group Delay (Decimator) = 3
× (32–1)/2 × (1/2.048e6)
= 22.7
s
If final filtering is implemented in the DSP, the final filter’s
group delay must be taken into account when calculating overall
group delay.
DESIGN CONSIDERATIONS
Analog Inputs
The AD73360 features six signal conditioning inputs. Each
signal conditioning block allows the AD73360 to be used with
either a single-ended or differential signal. The applied signal
can also be inverted internally by the AD73360 if required. The
analog input signal to the AD73360 can be dc-coupled, pro-
vided that the dc bias level of the input signal is the same as the
internal reference level (REFOUT). Figure 24 shows the recom-
mended differential input circuit for the AD73360. The circuit
of Figure 24 implements first-order low-pass filters with a 3 dB
VIN
TO INPUT BIAS
CIRCUITRY
VINPx
VINNx
REFOUT
REFCAP
VOLTAGE
REFERENCE
0.047 F
100
0.1 F
Figure 24. Example Circuit for Differential Input
(DC Coupling)
point at 34 kHz; these are the only filters that must be imple-
mented external to the AD73360 to prevent aliasing of the
sampled signal. Since the ADC uses a highly oversampled ap-
proach that transfers the bulk of the antialiasing filtering into the
digital domain, the off-chip antialiasing filter need only be of a
low order. It is recommended that for optimum performance the
capacitors used for the antialiasing filter be of high quality di-
electric (NPO).
The AD73360’s on-chip 38 dB preamplifier can be enabled
when there is not enough gain in the input circuit; the preampli-
fier is configured by bits IGS0–2 of CRD. The total gain must
be configured to ensure that a full-scale input signal produces a
signal level at the input to the sigma-delta modulator of the
ADC that does not exceed the maximum input range.
The dc biasing of the analog input signal is accomplished with
an on-chip voltage reference. If the input signal is not biased at
the internal reference level (via REFOUT), then it must be
ac-coupled with external coupling capacitors. CIN should be
0.1
F or larger. The dc biasing of the input can then be accom-
plished using resistors to REFOUT as in Figure 25.
VIN
TO INPUT BIAS
CIRCUITRY
VINPx
VINNx
REFOUT
REFCAP
VOLTAGE
REFERENCE
0.047 F
100
CIN
10k
0.047 F
0.1 F
Figure 25. Example Circuit for Differential Input
(AC Coupling)
Figures 26 and 27 detail ac- and dc-coupled input circuits for
single-ended operation respectively.
VIN
VINPx
VINNx
REFOUT
REFCAP
VOLTAGE
REFERENCE
100
CIN
10k
0.047 F
0.1 F
Figure 26. Example Circuit for Single-Ended Input
(AC Coupling)
VIN
VINPx
VINNx
REFOUT
REFCAP
VOLTAGE
REFERENCE
100
0.047 F
0.1 F
Figure 27. Example Circuit for Single-Ended Input
(DC Coupling)
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