參數(shù)資料
型號(hào)： AD6652BBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： 12-Bit, 65 MSPS IF to Baseband Diversity Receiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, BGA-256
文件頁(yè)數(shù)： 65/76頁(yè)
文件大?。?/td> 1839K
代理商： AD6652BBC
AD6652
Rev. 0 | Page 65 of 76
AGC
PROCESSED DATA
FROM RCFS
CHANNEL
INTERLEAVE
ENABLE/DISABLE
(0x08:3, 0x09:2)
BYPASS
(0x08:0, 0x09:0)
BYPASS
(0x0A:0, 0x12:0)
L
HALF-BAND
FILTER AND
2
×
INTERPOLATION
TO OUTPUT PORTS
A AND B
0
Figure 64. Block Diagram of an AGC Stage Showing the Components and Signal Routing Options
f AGC A shares the PIN SYNC
signed to
unter register at Address 0x0B
chooses not to use pin sync
s bit has a one-shot characteristic and does not
Bit 2 is set. Thi
need to be reset in order to respond to a new log
ic high being
written to it. Use of the sync now bit bypasses the AGC hold-off
counters; therefore, the name
Sync Now
.
When this bit is set, the CIC filter is cleared
umber of averaging
and new values for CIC decimation, n
samples, CIC scale, signal gain Gs, gain K,
are loaded. When Bit 2 = 0, the above-mentioned parameters
not updated and the CIC filter is not cleared. In both cases, a
AGC update sample is output from
decimator starts operating towards the next output sample
whenever a
Sync Now
occurs.
and pole parameter P
are
n
the CIC filter and the
nchronization signal might occur periodi-
applications, the sy
cally. If this bit is clear, each Pin_Sync resynchronizes the AGC.
If this bit is set, only the first sync high is recognized and
succeeding sync events are ignored until Bit 1 is reset.
ta
filters is still reduced to a
C
to
st be programmed with a 16-bit
dB from 0 to
used
in steps of 0.024 dB. A 12-bit
HB
Note: The hold-off counter o
assigned to DDC processing Channel 0. Therefore, if the user
intends to use the AGC A’s hold-off counter, the user must
attach the external sync signal to the pin sync that is as
DDC Channel 0. The hold-off co
for AGC A must be programmed with a 16-bit number that
corresponds to the desired delay before a new CIC decimated
value is updated. Writing a logic high to the proper pin sync pin
triggers the AGC hold-off counter with a retriggerable one-shot
pulse every time the pin is written high.
Bit 3 is the sync now bit. If the user
signals, the user can use the
Sync Now
command by program-
ming this bit high. This performs an immediate start of
decimation for a new update sample and initializes the AGC, if
Bit 2 is used to determine whether the AGC should initialize on
a
Sync Now
or not.
Bit 1 is used to ignore repetitive Pin_Sync signals. In some
Bit 0 is used to bypass the AGC section, when it is set. The da
from the interpolating half-band
lower bit width representation as set by Bits 7–5 of the AGC A
control register. A truncation at the output of the AGC
accomplishes this task.
0x0B: AGC A Hold-Off Counter
The AGC A hold-off counter is loaded with the 16-bit value
written to this address when
Sync Now
is written high or a
Pin_Sync is received. If this register is written to a 0, the AG
cannot be synchronized.
Note: The hold-off counter of AGC A shares the pin sync
assigned to DDC processing Channel 0. Therefore, if the user
intends to use AGC A’s hold-off counter, the user must either
attach the external sync signal to the pin sync that is assigned
DDC Channel 0 or use the software-controlled
Sync Now
function of Bit 3 at 0x0A.
The hold-off counter mu
number that corresponds to the desired delay before a new CIC
decimated value is updated. Writing a logic high to the proper
pin sync pin triggers the AGC hold-off counter with a
retriggerable one-shot pulse every time the pin is written high.
0x0C: AGC A Desired Level
This 8-bit register contains the desired output power level or
desired clipping level, depending on the mode of operation.
This desired request R level can be set in
23.99 dB, in steps of 0.094 dB. An 8-bit binary floating-point
representation is used with a 2-bit exponent followed by the
6-bit mantissa. The mantissa is in steps of 0.094 dB and the
exponent is in 6.02 dB steps. For example: 10’100101 represents
2 × 6.02 + 37 × 0.094 = 15.518 dB.
0x0D: AGC A Signal Gain
This register is used to set the initial value for a signal gain
in the gain multiplier. This 12-bit value sets the initial signal
gain between 0 and 96.296 dB
binary floating-point representation is used with a 4-bit
exponent followed by the 8-bit mantissa. For example:
0111’10001001 represents 7 × 6.02 + 137 × 0.024 = 45.428 dB.
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