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參數(shù)資料
| 型號(hào)： | AD6652BBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, BGA-256 |
| 文件頁數(shù)： | 59/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652BBC |
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AD6652
NCO control register at Channel Address 0x88. When this bit is
low, then the phase accumulator of the NCO is not cleared, but
starts to add the new NCO frequency word to the accumulator
as soon as
accumulator of the NCO is cleared to 0, and the new word is
then accumulated.
0x85: NCO Frequency Register 0
This register represents the 16 LSBs of the NCO frequency
word. These bits are shadowed and are
Rev. 0 | Page 59 of 76
the SYNC occurs. If this bit is high, then the phase
not updated to the
working register until the channel is either brought out of sleep
mode, or a Soft_SYNC or Pin_SYNC has been issued. In the
latter two cases, the register is updated when the frequency
es a value of 1. If the frequency
cy
as the shadow is written.
Memory Map
Register
Coefficient Memory (CMEM)
CHANNEL SLEEP
Soft_Sync Control Register
Pin_SYNC Control Register
Start Hold-Off Counter
NCO Frequency Hold-Off Counter
NCO Frequency Register 0
NCO Frequency Register 1
NCO Phase Offset Register
NCO Control Register
Unused
rCIC2 Decimation 1
rCIC2 Interpolation 1
rCIC2 Scale
Reserved
CIC5 Decimation 1
CIC5 Scale
Reserved
Unused
RCF Decimation 1
RCF Decimation Phase
RCF Number of Taps 1
RCF Coefficient Offset
Bit Wid
20
1
2
3
16
16
16
16
16
9
12
9
12
8
8
5
8
8
8
8
8
Table 24. Channel Address
Channel Address
00–7F
80
81
82
83
84
85
86
87
88
89–8F
90
91
92
93
94
95
96
97–9F
A0
A1
A2
A3
hold-off counter count reach
hold-off counter value is set to a value of 1, then the register is
updated as soon as the shadow is written.
0x86: NCO Frequency Register 1
This register represents the 16 MSBs of the NCO frequency
word. These bits are shadowed and are not updated to the
working register until the channel is either brought out of sleep
mode, or a Soft_SYNC or Pin_SYNC has been issued. In the
latter two cases, the register is updated only when the frequen
hold-off counter count reaches a value of 1. If the frequency
hold-off counter is set to a value of 1, then the register is
updated as soon
th
Comments
128 x 20-bit memory
0:
Sleep bit from EXT_ADDRESS 3
1:
Hop
0:
Start
2:
First SYNC only
1:
Hop_En
0:
Start_En
Start hold-off value
NCO_FREQ hold-off value
NCO_FREQ[15:0]
NCO_FREQ[31:16]
NCO_PHASE[15:0]
8-7:
SYNC input select
00 = A, 01 = B, 10 = C, 11 = D
6:
Input port select B or A, 0 = A, 1 = B
5-4:
Reserved, write both bits logic low
3:
Clear phase accumulator on hop
2:
Amplitude dither
1:
Phase dither
0:
Bypass (A-input -> I-path, B -> Q)
M
rCIC2
1
L
rCIC2
1
11:
Reserved, write to logic low
10:
Reserved, write to logic low
9-5:
rCIC2 _QUIET [4
4-0:
rCIC2_LOUD [4:0]
d (must be written low)
Reserve
M
CIC5
1
4-0:
CIC5_SCALE[4:0]
Reserved (must be written low)
M
RCF
1
P
RCF
N
Taps
1
CO
RCF
[1:0]
:0]
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相關(guān)代理商/技術(shù)參數(shù) |
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