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參數(shù)資料
| 型號： | AD6652 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機 |
| 文件頁數(shù)： | 9/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652 |
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AD6652
MICROPROCESSOR PORT TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
CLOAD = 40 pF on all outputs, unless otherwise specified.
Table 7.
MICROPROCESSOR PORT, MODE INM (MODE = 0)
MODE INM WRITE TIMING
t
SC
Control
1
to
↑
CLK Setup Time
t
HC
Control
1
to
↑
CLK Hold Time
t
HWR
WR(R/W) to RDY(DTACK) Hold Time
t
SAM
Address/Data to WR(R/W) Setup Time
t
HAM
Address/Data to RDY(DTACK) Hold Time
t
DRDY
WR(R/W) to RDY(DTACK) Delay
t
ACC
WR(R/W) to RDY(DTACK) High Delay
MODE INM READ TIMING
t
SC
Control
1
to
↑
CLK Setup Time
t
HC
Control
1
to
↑
CLK Hold Time
t
SAM
Address to RD(DS) Setup Time
t
HAM
Address to Data Hold Time
t
DRDY
RD(DS) to RDY(DTACK) Delay
t
ACC
RD(DS) to RDY(DTACK) High Delay
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
MODE MNM WRITE TIMING
t
SC
Control
1
to
↑
CLK Setup Time
t
HC
Control
1
to
↑
CLK Hold Time
t
HDS
DS(RD) to DTACK(RDY) Hold Time
t
HRW
R/W(WR) to DTACK(RDY) Hold Time
t
SAM
Address/Data To R/W(WR) Setup Time
t
HAM
Address/Data to R/W(WR) Hold Time
t
DDTACK
DS(RD) to DTACK(RDY) Delay
t
ACC
R/W(WR) to DTACK(RDY) Low Delay
MODE MNM READ TIMING
t
SC
Control
1
to
↑
CLK Setup Time
t
HC
Control
1
to
↑
CLK Hold Time
t
HDS
DS(RD) to DTACK(RDY) Hold Time
t
SAM
Address to DS(RD) Setup Time
t
HAM
Address to Data Hold Time
t
DDTACK
DS(RD) to DTACK(RDY) Delay
t
ACC
DS(RD) to DTACK(RDY) Low Delay
Rev. 0 | Page 9 of 76
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
2.0
2.5
7.0
3.0
5.0
8.0
4 × t
CLK
5.0
2.0
0.0
5.0
8.0
8 × t
CLK
Min
2.0
2.5
8.0
7.0
3.0
5.0
8.0
4 × t
CLK
5.0
2.0
8.0
0.0
5.0
8.0
8 × t
CLK
Typ
5 × t
CLK
10 × t
CLK
Typ
5 × t
CLK
10 × t
CLK
Max
9 × t
CLK
13 × t
CLK
Max
9 × t
CLK
13 × t
CLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Specification pertains to control signals: R/W, (WR), DS, (RD), and CS.
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