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參數(shù)資料
| 型號： | AD6652 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機(jī) |
| 文件頁數(shù)： | 33/76頁 |
| 文件大小： | 1839K |
| 代理商： | AD6652 |
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AD6652
NUMERICALLY CON
FREQUENCY TRANSLATION TO BASEBAND
This processing stage comprises a digital tuner consisting
Rev. 0 | Page 33 of 76
TROLLED OSCILLATOR
of
two multipliers, I and Q, and a 32-bit complex numerically
contr lled oscillator (NCO). Each channel of the AD6652 has
pendent NCO. The NCO serves as a quadrature local
r capable of producing an NCO frequency between
oscillato
CLK
/2 and
+CLK
/2 with a resolution of CLK/2
32
in the complex
mode. The worst-case spurious signal from the NCO is better
than 100 dBc for all output frequencies.
86 is
signed integer. Use the following
e NCO frequency:
an inde
The NCO frequency programmed in Registers 0x85 and 0x
interpreted as a 32-bit un
equation to calculate th
×
=
CLK
f
FREQ
NCO
32
2
_
where:
NCO_FREQ
is a decimal number equal to the 32-bit binary
ed at 0x85 and 0x86.
number to be programm
CLK
is the AD6652 DDC master clock rate (in Hz).
A shadow register generally precedes an active register. It holds
the next number to be used by the active egister whenever that
function’s hold-off counter causes the active register to be
updated with the new value. Active registers are also updated
with the contents of a shadow register any time the channel is
brought out of sleep mode.
-
ort.
ly from
’s
ER
lly
cy
)
arts counting down at the DDC CLK rate and, when it reaches
one, the new frequency value in the shadow register is written to
the active NCO frequency register.
etting
es.
cy u
E
E
e pha
e phas
eted as a 16-bit
rrespo
2π ra
nchro
e dif
phas
et r
mu
(0
f t
ed
, an
ster
e o
dd
O. This 16-b
r. A 0x0000 in this reg
FF
res
m
NC
wi
stan
utputs
th con
gra
le o
ter
o
r-
no
Th
p
ces.
to
be
et
O C
he
ures
Th
ass
IS
gis
ich
con
NC
atu
nt
88
n
ollo
igu
han
sect
n
To bypass the NCO of the AD6652, set Bit 0 of 0x88 high. When
the NCO is bypassed, down-con ersion is not performed, and
v
the AD6652 channel functions simply as a real filter on comp
data. This feature is useful for baseband sampling applications,
where the A input is connected to the I signal path within the
filter and the B input is connected to the Q signal path. Bypass
ing the NCO might be desired, if the
lex
-
digitized signal has already
been converted to baseband in prior analog stages or by other
digital preprocessing.
Phase Dither
The AD6652 provides a phase dither option for improving the
spurious performance o
Bit 1 of Register 0x88, which causes discrete spurs due to phase
truncation in the NCO to be randomized. The energy from
these spurs is spread into th
f the NCO. To enable phase dither, set
e noise floor and spurious free
dynamic range is increased at the expense of slight decreases in
the SNR. The choice of whether to use phase dither in a sy
depends ultimately on the system goals. If lower sp
desired at the expense of a slightly raised noise flo
dither should be employed. If the lowest noise floor is desired
and higher spurs can be tolerated or filtered by subsequen
stages, then phase dither is not needed.
Amplitude Di
stem
urs are
or, then phase
t
ther
Amplitude dither can also be used to improve spurious
performance of the NCO. To enable amplitude dither, set Bit 2
of 0x88, which causes amplitude quantization errors to be
randomized within the angular-to-Cartesian conversion stage
of the NCO. This option reduces spurs at the expense of a
slightly raised noise floor and slightly reduced SNR. Amplitude
dither and phase dither can be used together, separately, or not
at all.
f
is the desired NCO output frequency in Hz.
NCO SHADOW REGISTER
r
The NCO shadow register is updated during normal program
ming of the registers through the microport or serial input p
The active frequency register can receive update data on
the NCO shadow register. When software reads back an NCO
frequency, it is reading back the active frequency register and
not the shadow register.
NCO FREQUENCY HOLD-OFF REGIST
When the NCO frequency registers are written, data is actua
passed to a shadow register. Data can be moved to the active
register by one of two methods: when the channel comes out of
sleep mode or when a SYNC hop occurs. As a result of either
event, a count-down counter is loaded with an NCO frequen
hold-off value. The 16-bit unsigned integer counter (0x84
st
The NCO can be set up to update its frequency immediately
upon receipt of a HOP_SYNC or START_SYNC, with no
hold-off count, by setting the hold-off count value to 1. S
the hold-off count to zero prevents any frequen
pdat
PHAS OFFS T
Th
se offs
th
e accu
pr
co
nds to
of
dians.
sy
nized to roduc
feren
egister
lator o he NC
unsign
offset
is regi
x87) a
s a pro
mmab
it regis
ffset t
is inte
ister
an offs
intege
d a 0x
allows
FF cor
ultiple
ponds
Os to
t and k own
NC
Use t
feat
basis.
Byp
ONTR L REG TER
NCO
trol re
of the
O, wh
ese fe
res are described i the f
ter loca d at 0x
are co rolled o a per c
to conf
re the
nel
ions.
wing
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