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參數(shù)資料
| 型號： | AD6652 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機 |
| 文件頁數(shù)： | 12/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652 |
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AD6652
Table 10. Pin Function Descriptions
Pin No.
POWER SUPPLY
A13, B13, C13, D13, E13, F13, G13, H13, J13, K13, L13, M13, N13, P13, R13,
T13, A14, B14, C14, D14, E14, M14, N14, P14, R14
D4, D5, D6, D7, E4, E5, E6, E7, M8, M9, M10, M11, N8, N9, N10, N11
D8, D9, D10, D11, D12, E8, E9, E10, E11, E12, F12, G12, H12, J12, K12, L12,
M4, M5, M6, M7, M12, N4, N5, N6, N7, N12, P6
A1, B5, F2, F4, F5, F6, F7, F8, F9, F10, F11, G4, G5, G6, G7, G8, G9, G10, G11,
H4, H5, H6, H7, H8, H9, H10, H11, J2, J3, J4, J5, J6, J7, J8, J9, J10, J11, K4,
K5, K6, K7, K8, K9, K10, K11, L3, L4, L5, L6, L7, L8, L9, L10, L11, P1, T1
A15, A16, B15, B16, C15, D15, E15, E16, F14, F15, F16, G14, H14, H15, J14,
J15, K14, L14, L15, L16, M15, M16, N15, P15, R15, R16, T15, T16
MISCELLANEOUS
E3, P9, P10, P12, R7, R8, R9, R10, R11, T7, T8, T9, T10
B1
Pin No.
Mnemonic
ADC INPUTS
P16
VIN+A
N16
VINA
C16
VIN+B
D16
VINB
J16
VREF
H16
SENSE
T14
ACLK
B12
DUTYEN
A12, R12
PDWN
1
T12
SHRDREF
ADC OUTPUTS
A11
OTRA
P11
OTRB
K16
REFTA
G16
REFTB
K15
REFBA
G15
REFBB
DDC INPUTS
A8
RESET
T11
DCLK
T2
PCLK
D3
PACH1_LACLKIN
2
Rev. 0 | Page 12 of 76
Mnemonic
Type
Function
AVDD
Power
3.0 V Analog Supply, 25 Pins.
VDD
VDDIO
Power
Power
2.5 V Digital Core Supply, 16 Pins.
3.3 V Digital I/O Supply, 27 Pins.
DGND
Ground
Digital Ground, 56 Pins.
AGND
Ground
Analog Ground, 28 Pins.
NC
DNC
N/A
N/A
No Connect, 13 Pins.
Do Not Connect.
Type
Function
Input
Input
Input
Input
I/O
Input
Input
Input
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin () for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin () for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select.
ADC Master Clock.
Duty Cycle Stabilizer, Active High.
Power-Down Enable, Active High.
Shared Voltage Reference Select, Low = Independent, High = Shared.
Output
Output
Output
Output
Output
Output
Out-of-Range Indicator for Channel A, High = Overrange.
Out-of-Range Indicator for Channel B, High = Overrange.
Top Reference Voltage, Channel A.
Top Reference Voltage, Channel B.
Bottom Reference Voltage, Channel A.
Bottom Reference Voltage, Channel B.
Input
Input
I/O
I/O
Master Reset, Active Low.
DDC Master Clock.
Link Port Clock Output or Parallel Port Clock Input.
Channel ID Output Bit, MSB, for Parallel Port A, or Link Port A Data Ready Input.
Function depends on logic state of 0x1B:7 of output port control register.
Channel ID Output Bit, MSB, for Parallel Port B, or Link Port B Data Ready Input.
Function depends on logic state of 0x1D:7 of output port control register.
Hardware Sync, Pin A, Routed to All Receiver Channels.
Hardware Sync, Pin B, Routed to All Receiver Channels.
Hardware Sync, Pin C, Routed to All Receiver Channels.
Hardware Sync, Pin D, Routed to All Receiver Channels.
Chip ID Selector, Four Pins, Used in Conjunction with Access Control Register
Bits 5–2.
N2
PBCH1_LBCLKIN
2
I/O
B10
C10
B9
A10
K3, J1, M1,
K1
SYNCA
3
SYNCB
3
SYNCC
3
SYNCD
3
CHIP_ID[3:0]
3
Input
Input
Input
Input
Input
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