參數(shù)資料
型號： 9S12E128DGV1
廠商： Motorola, Inc.
英文描述： MC9S12E-Family Device User Guide V01.04
中文描述： MC9S12E -系列設(shè)備的用戶手冊V01.04
文件頁數(shù)： 97/156頁
文件大小： 3077K
代理商： 9S12E128DGV1
97
5.3.1 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states. Refer to the HCS12 MEBI Block Guide for mode
dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
Refer to
Table 1-1
for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the CPU12 Reference Manual for information about the Central Processing Unit.
When the CPU12 Reference Manual refers to
cycles
this is equivalent to
Bus Clock periods
.
So
1 cycle
is equivalent to
1 Bus Clock period
.
6.2 HCS12 Background Debug Module (BDM) Block Description
Consult the HCS12 BDM Block Guide for information about the Background Debug Module.
When the BDM Block Guide refers to
alternate clock
this is equivalent to
Oscillator Clock
.
6.3 HCS12 Debug (DBG) Block Description
Consult the HCS12 DBG Block Guide for information about the Debug module.
6.4 HCS12 Interrupt (INT) Block Description
Consult the HCS12 INT Block Guide for information about the Interrupt module.
6.5 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the HCS12 MEBI Block Guide for information about the Multiplexed External Bus Interface
module.
COP Watchdog Reset
3
CRG Module
$FFFA, $FFFB
Table 5-2 Reset Summary
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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