參數(shù)資料
型號(hào)： 9S12E128DGV1
廠商： Motorola, Inc.
英文描述： MC9S12E-Family Device User Guide V01.04
中文描述： MC9S12E -系列設(shè)備的用戶手冊(cè)V01.04
文件頁數(shù)： 100/156頁
文件大?。?/td> 3077K
代理商： 9S12E128DGV1
Device User Guide — 9S12E128DGV1/D V01.04
100
Description
There are three Serial Communications Interface modules (SCI0, SCI1, SCI2). Consult the SCI Block
Guide for information about the Serial Communications Interface module.
Section 17 Serial Peripheral Interface (SPI) Block
Description
Consult the SPI Block Guide for information about the Serial Peripheral Interface module.
Section 18 Timer (TIM) Block Description
There are three timer modules (TIM0, TIM1, TIM2). Consult the TIM_16B4C Block Guide for
information about the Timer module.
Section 19 Voltage Regulator (VREG) Block Description
Consult the VREG Block Guide for information about the dual output linear voltage regulator.
19.1 VREGEN
On the MC9S12E-Family the regulator enable signal (VREGEN) is not available externally and is
connected internally to VDDR.
19.2 VDD1, VDD2, VSS1, VSS2
In both the 112 pin LQFP and the 80 pin QFP package versions, both internal VDD and VSS of the 2.5V
domain are bonded out on 2 sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1
and VDD2 are connected together internally. VSS1 and VSS2 are connected together internally. This
allows systems to employ better supply routing and further decoupling.
Section 20 Printed Circuit Board Layout Proposals
The Printed Circuit Board (PCB) must be carefully laid out to ensure proper operation of the voltage
regulator as well as the MCU itself. The following rules must be observed:
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 - C6).
F
For More Information On This Product,
Go to: www.freescale.com
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.
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