參數(shù)資料
型號(hào)： 9S12E128DGV1
廠商： Motorola, Inc.
英文描述： MC9S12E-Family Device User Guide V01.04
中文描述： MC9S12E -系列設(shè)備的用戶手冊(cè)V01.04
文件頁數(shù)： 140/156頁
文件大?。?/td> 3077K
代理商： 9S12E128DGV1
Device User Guide — 9S12E128DGV1/D V01.04
140
B.7.2 ATD Operating Characteristics - 3.3V Range
The
Table B-11
shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA
≤
VRL
≤
VIN
≤
VRH
≤
VDDA
.
This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
Table B-11 3.3V ATD Operating Characteristics
Conditions are shown in
Table A-4
unless otherwise noted; Supply Voltage 3.3V-10% <= V
DDA
<= 3.3V+10%
B.7.3 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
B.7.3.1 Source Resistance:
Due to the input pin leakage current as specified in
Table A-6
and
Table A-7
in conjunction with the
source resistance there will be a voltage drop from the signal source to the ATD input. The maximum
source resistance R
S
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage
current. If device or operating conditions are less than worst case or leakage-induced error is acceptable,
larger values of source resistance are allowed.
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
D
Reference Potential
Low
High
V
RL
V
RH
V
SSA
V
DDA
/2
3.0
V
DDA
/2
V
DDA
3.6
V
V
2
C Differential Reference Voltage
V
RH
-V
RL
f
ATDCLK
3.3
V
3
D ATD Clock Frequency
0.5
2.0
MHz
4
D
ATD 10-Bit Conversion Period
Clock Cycles
1
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
Conv, Time at 4.0MHz
2
ATD Clock f
ATDCLK
NOTES
:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
2. Reduced accuracy see
Table B-13
and
Table B-14
.
N
CONV10
T
CONV10
T
CONV10
14
7
3.5
28
14
7
Cycles
μ
s
μ
s
5
D
ATD 8-Bit Conversion Period
Clock Cycles
(1)
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
N
CONV8
T
CONV8
12
6
26
13
Cycles
μ
s
6
D Recovery Time (V
DDA
=3.3 Volts)
t
REC
20
μ
s
7
P
Reference Supply current
I
REF
0.250
mA
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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