參數(shù)資料
型號(hào)： 9LPRS462AGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 240 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-8
文件頁(yè)數(shù)： 20/23頁(yè)
文件大?。?/td> 248K
代理商： 9LPRS462AGLFT
ICS9LPRS462
Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs
IDTTM/ICSTM
Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs
1378A—04/07/08
6
AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Crossing Point Variation
V
CROSS
Single-ended Measurement
140
mV
1,2,5
Frequency
f
Spread Specturm On
198.8
200
MHz
1,3
Long Term Accuracy
ppm
Spread Specturm Off
-300
+300
ppm
1,11
Rising Edge Slew Rate
SRISE
Differential Measurement
0.5
10
V/ns
1,4
Falling Edge Slew Rate
SFALL
Differential Measurement
0.5
10
V/ns
1,4
Slew Rate Variation
tSLVAR
Single-ended Measurement
20
%
1
CPU, DIF HTT Jitter - Cycle to
Cycle
CPUJC2C
Differential Measurement
150
ps
1,6
Accumulated Jitter
tJACC
See Notes
1
ns
1,7
Peak to Peak Differential Voltage
VD(PK-PK)
Differential Measurement
400
2400
mV
1,8
Differential Voltage
VD
Differential Measurement
200
1200
mV
1,9
Duty Cycle
DCYC
Differential Measurement
45
55
%
1
Amplitude Variation
V
D
Change in VD DC cycle to cycle
-75
75
mV
1,10
CPU Skew
CPUSKEW10
Differential Measurement
100
ps
1
Guaranteed by design and characterization, not 100% tested in production.
Minimum Frequency is a result of 0.5% down spread spectrum
6 Max difference of t
CYCLE between any two adjacent cycles.
7 Accumulated tjc.over a 10 s time period, measured with JIT2 TIE at 50ps interval.
8 VD(PK-PK) is the overall magnitude of the differential signal.
11 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
9
VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V VD.
VD(max) is the largest amplitude allowed.
10 The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of
the signal.
Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is not
important due to the blocking cap.
Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate spec when
crossing through this region.
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK
and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
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