參數(shù)資料
型號(hào)： 72T3655L5BBGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： FIFO
英文描述： 2K X 36 OTHER FIFO, 3.6 ns, PBGA208
封裝： 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-208
文件頁(yè)數(shù)： 52/57頁(yè)
文件大?。?/td> 472K
代理商： 72T3655L5BBGI
56
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T3645 can easily be adapted to applications requiring depths
greater than 1,024, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665,
8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the
IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115
and 262,144 for the IDT72T36125 with an 18-bit bus width. In FWFT mode,
theFIFOscanbeconnectedinseries(thedataoutputsofoneFIFOconnected
to the data inputs of the next) with no external logic necessary. The resulting
configuration provides a total depth equivalent to the sum of the depths
associated with each single FIFO. Figure 37 shows a depth expansion using
two IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain – no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the
datawordappearsattheoutputsofoneFIFO,thatdevice's
ORlinegoesLOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for
ORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock, for the
OR flag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFO of the chain, that FIFO's
IRlinegoesLOW,enablingtheprecedingFIFO
to write a word to fill it.
Forafullexpansionconfiguration,theamountoftimeittakesfor
IRofthefirst
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock, for the
IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
end of the chain and free locations to the beginning of the chain.
Figure 37. Block Diagram of 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36, 262,144 x 36 and 524,288 x 36
Depth Expansion
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
5907 drw42
n
FWFT/SI
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
RCS
READ CHIP SELECT
RCS
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
相關(guān)PDF資料
PDF描述
72V275L15PF8 32K X 18 OTHER FIFO, 10 ns, PQFP64
72V285L10PF8 64K X 18 OTHER FIFO, 6.5 ns, PQFP64
72V285L15TFI9 64K X 18 OTHER FIFO, 10 ns, PQFP64
72V3626L15PFG 256 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
72V3684L15PF 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
72T3655L5BBI 功能描述:IC FIFO 2048X36 5NS 208-BGA 制造商:idt, integrated device technology inc 系列:72T 包裝:托盤(pán) 零件狀態(tài):過(guò)期 存儲(chǔ)容量:72K（2K x 36） 功能:異步，同步 數(shù)據(jù)速率:83MHz，200MHz 訪問(wèn)時(shí)間:10ns，3.6ns 電壓 - 電源:2.375 V ~ 2.625 V 電流 - 電源（最大值）:70mA 總線方向:單向 擴(kuò)充類(lèi)型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:208-BGA 供應(yīng)商器件封裝:208-PBGA（17x17） 標(biāo)準(zhǔn)包裝:15
72T3655L6-7BB 功能描述:IC FIFO 2048X36 6-7NS 208-BGA 制造商:idt, integrated device technology inc 系列:72T 包裝:托盤(pán) 零件狀態(tài):過(guò)期 存儲(chǔ)容量:72K（2K x 36） 功能:異步，同步 數(shù)據(jù)速率:66MHz，150MHz 訪問(wèn)時(shí)間:12ns，3.8ns 電壓 - 電源:2.375 V ~ 2.625 V 電流 - 電源（最大值）:70mA 總線方向:單向 擴(kuò)充類(lèi)型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:208-BGA 供應(yīng)商器件封裝:208-PBGA（17x17） 標(biāo)準(zhǔn)包裝:15
72T3665L4-4BB 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72T3665L4-4BBG 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72T3665L5BB 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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