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參數(shù)資料
| 型號： | 72T3655L5BBGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 2K X 36 OTHER FIFO, 3.6 ns, PBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 45/57頁 |
| 文件大?。?/td> | 472K |
| 代理商： | 72T3655L5BBGI |
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5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
DESCRIPTION (CONTINUED)
ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol
inputs, MARK and ,
RT(Retransmit).IftheMARKinputisenabledwithrespect
to the RCLK, the memory location being read at that point will be marked. Any
subsequent retransmit operation,
RTgoesLOW,willresetthereadpointerto
this‘marked’location.
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread
out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe
FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
is configured during master reset by the state of the Big-Endian (
BE)pin.See
Figure 5 for Bus-Matching Byte Arrangement.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (
OE) and Synchronous Read
Chip Select pin (
RCS)areprovidedontheFIFO.TheSynchronousReadChip
SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
The TeraSync FIFO has the capability of operating its ports (write and/or
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input SHSTL is also provided, this allows the user
to select HSTL operation for other pins on the device (not associated with the
write or read ports).
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 are fabricated using IDT’s high speed sub-
micron CMOS technology.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72T3655L5BBI | 功能描述:IC FIFO 2048X36 5NS 208-BGA 制造商:idt, integrated device technology inc 系列:72T 包裝:托盤 零件狀態(tài):過期 存儲容量:72K（2K x 36） 功能:異步，同步 數(shù)據(jù)速率:83MHz，200MHz 訪問時間:10ns，3.6ns 電壓 - 電源:2.375 V ~ 2.625 V 電流 - 電源（最大值）:70mA 總線方向:單向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:208-BGA 供應商器件封裝:208-PBGA（17x17） 標準包裝:15 |
| 72T3655L6-7BB | 功能描述:IC FIFO 2048X36 6-7NS 208-BGA 制造商:idt, integrated device technology inc 系列:72T 包裝:托盤 零件狀態(tài):過期 存儲容量:72K（2K x 36） 功能:異步，同步 數(shù)據(jù)速率:66MHz，150MHz 訪問時間:12ns，3.8ns 電壓 - 電源:2.375 V ~ 2.625 V 電流 - 電源（最大值）:70mA 總線方向:單向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BGA 供應商器件封裝:208-PBGA（17x17） 標準包裝:15 |
| 72T3665L4-4BB | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72T3665L4-4BBG | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72T3665L5BB | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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