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參數(shù)資料
| 型號(hào)： | 30144-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, PBGA352 |
| 封裝： | BGA-352 |
| 文件頁(yè)數(shù)： | 97/247頁(yè) |
| 文件大?。?/td> | 4365K |
| 代理商： | 30144-23 |
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Revision 1.1
97
www.national.com
Integrated Functions (
Continued
)
G
4.1
The GXLV processor
’
s integrated functions programming
interface is a memory mapped space. The control regis-
ters for the graphics pipeline, display controller, and mem-
ory controller are located in this space, as well as all the
graphics memory: frame buffer, compression buffer etc.
This memory address space is referred to as the GXLV
processor memory space.
INTEGRATED FUNCTIONS PROGRAMMING INTERFACE
4.1.1
The base address for these memory mapped registers is
programmed in the Graphics Configuration Register
(GCR, Index B8h, bits[1:0]), shown in Table 4-1. The GCR
only specifies address bits [31:30] of physical memory.
The remaining address bits [29:0] are fixed to zero. The
GCR is I/O mapped because it must be accessed before
memory mapping can be enabled. Refer to Section
3.3.2.2
“
Configuration Registers
”
on page 50 for informa-
tion on how to access this register.
Graphics Control Register
The GXLV processor incorporates graphics functions that
require registers to implement and control them. Most of
these registers are memory mapped and physically
located in the logical units they control. The mapping of
these units is controlled by the GCR register.
Figure 4-2 shows the complete memory address map for
the GXLV processor. When accessing the GXLV proces-
sor memory space, address bits [29:24] must be zero.
This means that the GXLV processor accesses a linear
address space with a total of 16 MB. Address bit 23
divides this space into 8 MB for control (bit 23 = 0) and 8
MB for graphics memory (bit 23 = 1). In control space, bits
[22:16] are not decoded, so the programmer should set
them to zero. Address bit 15 divides the remaining 64 KB
address space into scratchpad RAM and PCI access (bit
15 = 0) and control registers (bit 15 = 1). Note that
scratchpad RAM is placed here by programming the tags
appropriately.
Device drivers are responsible for performing physical-to-
virtual memory-address translation, including allocation of
selectors that point to the GXLV processor. All memory
decoded by the processor may be accessed in protected
mode by creating a selector with the physical address
equal to the GXLV Base Address which is shown in Table
4-1, and a limit of 16 MB. Additionally, a selector with only
a 64 KB limit is large enough to access all of the GXLV
processor
’
s registers and scratchpad RAM.
Table 4-1. GCR Register
Bit
Name
Description
Index B8h
GCR Register (R/W)
Default Value = 00h
7:4
3:2
RSVD
SP
Reserved:
Set to 0.
Scratchpad Size:
Specifies the size of the scratchpad cache.
00 = 0 KB; Graphics instruction disabled (see Section 4.1.5
“
Display Driver Instructions
”
on page 102).
01 = 2 KB
10 = 3 KB
11 = 4 KB
GXLV Base Address:
Specifies the physical address for the base (GX_BASE) of the scratchpad RAM, the
graphics memory (frame buffer, compression buffer, etc.) and the other memory mapped registers.
00 = Scratchpad RAM, Graphics Subsystem, and memory-mapped configuration registers are disabled.
01 = Scratchpad RAM and control registers start at GX_BASE = 40000000h.
10 = Scratchpad RAM and control registers start at GX_BASE = 80000000h.
11 = Scratchpad RAM and control registers start at GX_BASE = C0000000h.
1:0
GX
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