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參數(shù)資料
| 型號(hào)： | 30144-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, PBGA352 |
| 封裝： | BGA-352 |
| 文件頁數(shù)： | 79/247頁 |
| 文件大?。?/td> | 4365K |
| 代理商： | 30144-23 |
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Revision 1.1
79
www.national.com
Processor Programming (
Continued
)
G
3.6
The processing of either an interrupt or an exception
changes the normal sequential flow of a program by trans-
ferring program control to a selected service routine.
Except for SMM interrupts, the location of the selected
service routine is determined by one of the interrupt vec-
tors stored in the interrupt descriptor table.
INTERRUPTS AND EXCEPTIONS
True interrupts are hardware interrupts and are generated
by signal sources external to the CPU. All exceptions
(including so-called software interrupts) are produced inter-
nally by the CPU.
3.6.1
External events can interrupt normal program execution
by using one of the three interrupt pins on the GXLV pro-
cessor:
Interrupts
Non-maskable Interrupt (No pin, see note)
Maskable Interrupt (INTR pin)
SMM Interrupt (SMI# pin)
Note:
There is not an NMI pin on the GXLV processor.
Generation of an NMI interrupt is not possible. However,
software can generate an NMI by setting bit 2 of CCR7.
(See the CCR7 register on page 53.)
For most interrupts, program transfer to the interrupt rou-
tine occurs after the current instruction has been com-
pleted. When the execution returns to the original
program, it begins immediately following the interrupted
instruction.
The
NMI interrupt
cannot be masked by software and
always uses interrupt vector two to locate its service rou-
tine. Since the interrupt vector is fixed and is supplied
internally, no interrupt acknowledge bus cycles are per-
formed. This interrupt is normally reserved for unusual sit-
uations such as parity errors and has priority over INTR
interrupts.
Once NMI processing has started, no additional NMIs are
processed until an IRET instruction is executed, typically
at the end of the NMI service routine. If the NMI is re-
asserted before execution of the IRET instruction, one
and only one NMI rising edge is stored and then pro-
cessed after execution of the next IRET.
During the NMI service routine, maskable interrupts may
be enabled. If an unmasked INTR occurs during the NMI
service routine, the INTR is serviced and execution
returns to the NMI service routine following the next IRET.
If a HALT instruction is executed within the NMI service
routine, the CPU restarts execution only in response to
RESET, an unmasked INTR or a System Management
Mode (SMM) interrupt. NMI does not restart CPU execu-
tion under this condition.
The
INTR interrupt
is unmasked when the Interrupt
Enable Flag (IF, bit 9) in the EFLAGS register is set to 1
(See the EFLAGS Register in Table 3-4 on page 46).
Except for string operations, INTR interrupts are acknowl-
edged between instructions. Long string operations have
interrupt windows between memory moves that allow
INTR interrupts to be acknowledged.
When an INTR interrupt occurs, the CPU performs an
interrupt-acknowledge bus cycle. During this cycle, the
CPU reads an 8-bit vector that is supplied by an external
interrupt controller. This vector selects which of the 256
possible interrupt handlers will be executed in response to
the interrupt.
The
SMM interrupt
has higher priority than either INTR or
NMI. After SMI# is asserted, program execution is passed
to an SMM service routine that runs in SMM address
space reserved for this purpose. The remainder of this
section does not apply to the SMM interrupts. SMM inter-
rupts are described in greater detail later in Section 3.7
“
System Management Mode
”
on page 83.
3.6.2
Exceptions are generated by an interrupt instruction or a
program error. Exceptions are classified as traps, faults or
aborts depending on the mechanism used to report them
and the restartability of the instruction which first caused
the exception.
Exceptions
A
Trap exception
is reported immediately following the
instruction that generated the trap exception. Trap excep-
tions are generated by execution of a software interrupt
instruction (INTO, INT3, INTn, BOUND), by a single-step
operation or by a data breakpoint.
Software interrupts can be used to simulate hardware
interrupts. For example, an INTn instruction causes the
processor to execute the interrupt service routine pointed
to by the nth vector in the interrupt table. Execution of the
interrupt service routine occurs regardless of the state of
the IF flag (bit 9) in the EFLAGS register.
The one byte INT3, or breakpoint interrupt (vector 3), is a
particular case of the INTn instruction. By inserting this
one byte instruction in a program, the user can set break-
points in the code that can be used during debug.
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