17
CHAPTER 1 GENERAL
Table 1-6. Functional Outline of
μ
PD78078Y Subseries
Item
Part Number
Mask ROM
PROM
48K bytes
60K bytes
60K bytes
Note 1
1024 bytes
32 bytes
1024 bytes
64K bytes
8 bits
×
8
×
4 banks
0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s/6.4
μ
s/12.8
μ
s (at 5.0 MHz)
122
μ
s (at 32.768 kHz)
16-bit operation
Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjustment, etc.
Total
CMOS input
CMOS I/O
N-ch open-drain I/O : 8
: 88
: 2
: 78
8-bit resolution
×
8 channels
8-bit resolution
×
2 channels
3-wire serial I/O/2-wire serial I/O/I
2
C bus mode selectable
3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes)
: 1 channel
3-wire serial I/O/UART mode selectable
: 1 channel
: 1 channel
16-bit timer/event counter : 1 channel
8-bit timer/event counter : 4 channels
Watch timer
Watchdog timer
: 1 channel
: 1 channel
5 (14-bit PWM output: 1, 8-bit PWM output: 2)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with
main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)
Internal: 15, external: 7
Internal: 1
1
Internal: 1, external: 1
V
DD
= 1.8 to 5.5 V
100-pin plastic QFP (14
×
20 mm, resin thickness 2.7 mm)
100-pin plastic LQFP (fine pitch) (14
×
14 mm, resin thickness 1.4 mm)
Note 2
100-pin ceramic WQFN (14
×
20 mm) (
μ
PD78P078Y only)
Notes 1.
The internal ROM capacity can be changed by using a memory size select register (IMS).
2.
Under development
ROM
High-speed RAM
Buffer RAM
Expansion RAM
Memory space
General-purpose register
Minimum
With main
instruction
system clock
execution With subsystem
time
clock
Instruction set
I/O port
A/D converter
D/A converter
Serial interface
Timer
Timer output
Clock output
Buzzer output
Vectored
Maskable
interrupt
Non-maskable
source
Software
Test input
Supply voltage
Package
Internal
memory
μ
PD78076Y
μ
PD78078Y
μ
PD78P078Y