86
CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION
Cautions 1. When an instruction that writes a value to the OSMS is executed (including when the
instruction is executed to write the same value), the main system clock cycle is extended up
to 2/f
X
only during the execution of the write instruction.
Consequently, a temporary error of the count clock cycle of the peripheral hardware units that
operate on the main system clock, such as timers, occurs.
2. Setting MCS to 0 is prohibited. On RESET input, however, OSMS is reset to 00H. Therefore,
be sure to set MCS to 1 at the start of a program or after clearing reset.
Figure 3-8. Format of Clock Select Register 1 (
μ
PD78098, 78098B subseries)
Caution Be sure to clear bits 2 through 7 to 0.
Figure 3-9. Format of Clock Select Register 2 (
μ
PD78098, 78098B subseries)
Caution Be sure to clear bits 1 through 7 to 0.
Figure 3-7. Format of Oscillation Mode Select Register (
μ
PD780018, 780018Y subseries)
7
6
5
4
3
2
Symbol
1
0
MCS
Controls divider circuit of main system clock
FFF2H
MCS
OSMS
0
0
0
0
0
0
0
Address
At reset
R/W
00H
W
0
Setting prohibited
1
Does not use divider circuit
7
6
5
4
3
2
Symbol
1
0
Controls divider circuit of main system clock (divider
circuit 1)
F8E0H
IECL10
IECL1
IECL11
0
0
0
0
0
0
Address
At reset
R/W
00H
R/W
IECL10
0
Uses 2/3 divider circuit in divider circuit 1
1
Does not use 2/3 divider circuit in divider circuit 1
Controls divider circuit of main system clock (divider
circuit 2)
IECL11
0
Uses 1/2 divider circuit in divider circuit 2
1
Does not use1/2 divider circuit in divider circuit 2
7
6
5
4
3
2
Symbol
1
0
Controls divider circuit of main system clock (divider
circuit 1)
F8E1H
IECL20
IECL2
0
0
0
0
0
0
0
Address
At reset
R/W
00H
R/W
IECL20
0
Uses 1/3 divider circuit in divider circuit 1
1
Does not use 1/3 divider circuit in divider circuit 1