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CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE
8.3.2 Application as slave CPU
A slave CPU receives addresses, commands, and data from the master CPU and transmits data to the master
CPU.
In the example shown in this section, addresses are received by using the wake-up function. This function is to
generate an interrupt only when the address value transmitted by the master to the slave coincides with the value
set to the slave address register (SVA) of the slave in the SBI mode. Therefore, only the slave CPU selected by the
master CPU generates INTCSI0, and the slave CPUs not selected operates without generating an inadvertent
interrupt request.
The slave CPU clears the wake-up function when it has been selected by the master (the interrupt request signal
is generated at the end of transmission), and interfaces with the master CPU. Addresses, commands, and data being
transmitted are identified by using bits 2 and 3 (RELD and CMDD) of the serial bus interface control register (SB IC).
Because the slave CPU is not automatically placed in the unselect status, a program that returns the slave CPU
to the unselect status must be prepared by processing commands between the master and CPU.
(1) Description of package
<Public declaration symbol>
RCVDAT: Receive data storage area
<Register used>
Bank 0: A
<RAM used>
Name
Usage
Attribute
Bytes
RCVDAT
Stores receive data
SADDR
1
<Flag used>
Name
Usage
RCVFLG
Sets reception mode
<Nesting>
1 level 3 bytes
<Hardware used>
Serial interface channel 0
<Initial setting>
Setting of serial interface channel 0
CSIM0=#10010011B;
Sets SBI mode, SBI pin, and wake-up mode, and inputs
serial clock from external source
Outputs synchronous busy signal
Makes SO0 latch high
Slave address
BYSE=1
RELT=1
SVA=#SLVADR;
Enables serial interface channel 0 interrupt