85
CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION
Figure 3-5. Format of Oscillation Mode Select Register
(
μ
PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y,
780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,
μ
PD78070A, 78070AY)
Cautions 1. When an instruction that writes a value to the OSMS is executed (including when the
instruction is executed to write the same value), the main system clock cycle is extended up
to 2/f
X
only during the execution of the write instruction.
Consequently, a temporary error of the count clock cycle of the peripheral hardware units that
operate on the main system clock, such as timers, occurs.
When the oscillation mode is changed, the clock supplied to the peripheral hardware, as well
as the clock supplied to the CPU, is changed.
It is therefore recommended that you execute the instruction to write the OSMS only once after
the reset signal has been deasserted, and before the peripheral hardware operates.
2. Set 1 to MCS after V
DD
has risen to 2.7 V or more.
Figure 3-6. Format of Oscillation Mode Select Register (
μ
PD78098, 78098B subseries)
Caution When an instruction that writes a value to the OSMS is executed (including when the instruction
is executed to write the same value), the main system clock cycle is extended up to 2/f
X
only during
the execution of the write instruction.
Consequently, `rary error of the count clock cycle of the peripheral hardware units that operate
on the main system clock, such as timers, occurs.
When the oscillation mode is changed, the clock supplied to the peripheral hardware, as well as
the clock supplied to the CPU, is changed.
It is therefore recommended that you execute the instruction to write the OSMS only once after
the reset signal has been deasserted, and before the peripheral hardware operates.
7
6
5
4
3
2
Symbol
1
0
MCS
Controls divider circuit of main system clock
FFF2H
MCS
OSMS
0
0
0
0
0
0
0
Address
At reset
R/W
00H
W
0
Uses divider circuit
1
Does not use divider circuit
7
6
5
4
3
2
Symbol
1
0
Controls divider circuit of main system clock (divider
circuit 1)
FFF2H
MCS
OSMS
0
0
0
0
0
0
0
Address
At reset
R/W
00H
W
0
Uses 1/2 divider circuit in divider circuit 1
1
Does not use 1/2 divider circuit in divider circuit 1
MCS