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參數(shù)資料
| 型號： | μPD45128441 |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-bit Synchronous DRAM(128M 同步DRAM) |
| 中文描述： | 128兆位同步DRAM（128M的同步DRAM）的 |
| 文件頁數(shù)： | 8/84頁 |
| 文件大小： | 693K |
| 代理商： | ΜPD45128441 |
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Preliminary Data Sheet
8
μ
PD45128441, 45128841, 45128163
CONTENTS
1.
Input / Output Pin Function ............................................................................................................ 10
2.
Commands ....................................................................................................................................... 11
3.
Simplified State Diagram ................................................................................................................. 14
4.
Truth Table ....................................................................................................................................... 15
4.1
Command Truth Table............................................................................................................................. 15
4.2
DQM Truth Table...................................................................................................................................... 15
4.3
CKE Truth Table....................................................................................................................................... 15
4.4
Operative Command Table ..................................................................................................................... 16
4.5
Command Truth Table for CKE .............................................................................................................. 19
5.
Initialization ...................................................................................................................................... 20
6.
Programming the Mode Register ................................................................................................... 21
7.
Mode Register .................................................................................................................................. 22
7.1
Burst Length and Sequence .................................................................................................................. 23
8.
Address Bits of Bank-Select and Precharge ................................................................................. 24
9.
Precharge ......................................................................................................................................... 25
10. Auto Precharge ................................................................................................................................ 26
10.1
Read with Auto Precharge ................................................................................................................... 26
10.2
Write with Auto Precharge .................................................................................................................. 27
11. Read / Write Command Interval ..................................................................................................... 28
11.1
Read to Read Command Interval ........................................................................................................ 28
11.2
Write to Write Command Interval ........................................................................................................ 28
11.3
Write to Read Command Interval ........................................................................................................ 29
11.4
Read to Write Command Interval ........................................................................................................ 30
12. Burst Termination ............................................................................................................................ 31
12.1
Burst Stop Command .......................................................................................................................... 31
12.2
Precharge Termination ........................................................................................................................ 32
12.2.1
12.2.2
Precharge Termination in READ Cycle .................................................................................... 32
Precharge Termination in WRITE Cycle .................................................................................. 33
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PD45128441G5 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| PD45128441G5-A10I-9JF | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| PD45128441G5-A10LI-9JF | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| PD45128441G5-A10LT-9JF | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| PD45128441G5-A10T-9JF | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
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