參數(shù)資料
型號(hào)： μPD45128441
廠商： NEC Corp.
英文描述： 128M-bit Synchronous DRAM(128M 同步DRAM)
中文描述： 128兆位同步DRAM（128M的同步DRAM）的
文件頁(yè)數(shù)： 10/84頁(yè)
文件大?。?/td> 693K
代理商： ΜPD45128441
Preliminary Data Sheet
10
μ
PD45128441, 45128841, 45128163
1. Input / Output Pin Function
Pin name
Input / Output
Function
CLK
Input
CLK is the master clock input. Other inputs signals are referenced to the CLK rising
edge.
CKE
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising
edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock
is not issued and the
μ
PD45128xxx suspends operation.
When the
μ
PD45128xxx is not in burst mode and CKE is negated, the device enters
power down mode. During power down mode, CKE must remain low.
/CS
Input
/CS low starts the command input cycle. When /CS is high, commands are ignored
but operations continue.
/RAS, /CAS, /WE
Input
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different
functions. For details, refer to the command table.
A0 - A13
Input
Row Address is determined by A0 - A13 at the CLK (clock) rising edge in the active
command cycle. It does not depend on the bit organization.
Column Address is determined by A0 - A9, A11 at the CLK rising edge in the read or
write command cycle. It depends on the bit organization : A0 - A9, A11 for
×
4 device,
A0 - A9 for
×
8 device, A0 - A8 for
×
16 device.
A12 and A13 are the bank select signal (BS). In command cycle, A12 and A13 low
select bank A, A12 low and A13 high select bank B, A12 high and A13 low select bank
C and then A12 and A13 high select bank D.
A10 defines the precharge mode. When A10 is high in the precharge command cycle,
all banks are precharged; when A10 is low, only the bank selected by A12 and A13 is
precharged.
When A10 is high in read or write command cycle, the precharge starts automatically
after the burst access.
DQM, UDQM,
LDQM
Input
DQM controls I/O buffers. In
×
16 products, UDQM and LDQM control upper byte and
lower byte I/O buffers, respectively.
In read mode, DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory cell if
DQM is low but not if DQM is high.
The DQM latency for the write is zero.
DQ0 - DQ15
Input / Output
DQ pins have the same function as I/O pins on a conventional DRAM.
V
CC
, V
SS
, V
CC
Q,
V
SS
Q
(Power supply)
V
CC
and V
SS
are power supply pins for internal circuits. V
CC
Q and V
SS
Q are power
supply pins for the output buffers.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PD45128441G5 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
PD45128441G5-A10I-9JF 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
PD45128441G5-A10LI-9JF 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
PD45128441G5-A10LT-9JF 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
PD45128441G5-A10T-9JF 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
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