參數(shù)資料
型號(hào): μPD45128441
廠商: NEC Corp.
英文描述: 128M-bit Synchronous DRAM(128M 同步DRAM)
中文描述: 128兆位同步DRAM(128M的同步DRAM)的
文件頁(yè)數(shù): 1/84頁(yè)
文件大?。?/td> 693K
代理商: ΜPD45128441
The information in this document is subject to change without notice.
1997
MOS INTEGRATED CIRCUIT
μ
PD45128441, 45128841, 45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
PRELIMINARY DATA SHEET
Document No. M12650EJ5V0DS00 (5th edition)
Date Published July 1998 NS CP (K)
Printed in Japan
The mark
shows major revised points.
Description
The
μ
PD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access
memories, organized as 8,388,608
×
4
×
4, 4,194,304
×
8
×
4, 2,097,152
×
16
×
4 (word
×
bit
×
bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by A12 and A13 (Bank Select)
Byte control (
×
16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
×
4,
×
8,
×
16 organization
Single 3.3 V
±
0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
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