參數(shù)資料
型號(hào): μPD45128441
廠商: NEC Corp.
英文描述: 128M-bit Synchronous DRAM(128M 同步DRAM)
中文描述: 128兆位同步DRAM(128M的同步DRAM)的
文件頁(yè)數(shù): 32/84頁(yè)
文件大?。?/td> 693K
代理商: ΜPD45128441
Preliminary Data Sheet
32
μ
PD45128441, 45128841, 45128163
12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
To issue a precharge command, t
RAS
must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Read
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 2
Q1
DQ
Command
Q2
Q3
Q4
ACT
t
RP
PRE
Hi-Z
(t
RAS
must be satisfied)
Read
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 3
DQ
Command
Q1
Q2
Q3
ACT
t
RP
PRE
Hi-Z
T8
Q4
(t
RAS
must be satisfied)
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