參數(shù)資料
型號: ZPSD601(V)E1
英文描述: Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,零功耗,4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞(可編程邏輯,零功耗,4K的位的SRAM,26余個(gè)可編程輸入/輸出,通用PLD的有63個(gè)輸入)
文件頁數(shù): 63/98頁
文件大?。?/td> 484K
代理商: ZPSD601(V)E1
ZPSD6XX(V) Family
12-63
Port Configuration
Reset
Power Down Mode
MCU I/O
Input
Unchanged
ZPLD Output
Active
Depends on inputs to the ZPLD
Address Out
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Register
Reset
Power Down Mode
PMMR0 & 1
Cleared (power up reset)
Unchanged (warm reset)
Unchanged
Micro
Cells Flip-Flop
Unchanged*
Unchanged*
All other registers
Cleared to “0”
Unchanged
Table 34. Chip Status During Reset and Power Down Mode
Power
Management
Unit
(cont.)
*
The Micro
Cell Flip-Flop can be cleared or set by the reset input or the PDN (Power Down) signal, depending on
the .re and .pr equations that are defined in the PSDabel file.
Battery Backup
The ZPSD6XX(V) supports a battery backup operation that retains the contents of the
SRAM in the event of a power loss. The Port PC2 pin is dedicated as the input pin for an
external power source. If the supply voltage falls below a reference voltage (Vstby), an inter-
nal power-switch occurs so that PC2 provides power to the internal SRAM. The SRAM
contents are retained down to a level of 2V.
Security Protection
The ZPSD6XX(V) has a programmable security bit which inhibits duplication. When the
bit is set, the contents of the EPROM, non-volatile configuration bits, and ZPLD cannot be
read by device programmers.
The security bit is set through the PSDsoft Software and is embedded in the compiled
output file. The security bit is UV erasable and a secured ZPSD6XX(V) in a windowed
package can be erased and re-programmed.
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