參數(shù)資料
型號(hào)： ZPSD601(V)E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，零功耗，4K的位的SRAM，26余個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入）
文件頁(yè)數(shù)： 4/98頁(yè)
文件大小： 484K
代理商： ZPSD601(V)E1
ZPSD6XX(V) Family
12-4
Upon each address or logic input change to the ZPSD, the device powers up from low
power standby for a short time. The ZPSD consumes only the necessary power to deliver
new logic or memory data to its outputs as a response to the input change. After the new
outputs are stable, the ZPSD latches them and automatically reverts back to standby mode.
The I
CC
current flowing during standby mode and during DC operation is identical and is
only a few microamperes.
The ZPSD automatically reduces its DC current drain to these low levels and does not
require controlling by the CSI (Chip Select) input. Disabling the CSI pin unconditionally
forces the ZPSD to standby mode independent of other input transitions.
The only significant power consumption in the ZPSD occurs during AC operation. The
ZPSD contains the first architecture to apply zero power techniques to memory circuit
blocks as well as logic.
Figure 2 compares ZPSD zero power operation to the operation of a discrete solution.
A standard microcontroller (MCU) bus cycle usually starts with an ALE (or AS) pulse and
the generation of an address. The ZPSD detects the address transition and powers up for a
very short time. The ZPSD then latches the outputs of the PAD, EPROM and SRAM to the
new values. After finishing these operations, the ZPSD shuts off its internal power and
enters standby mode. The time taken for the entire cycle is less than the ZPSD’s “access
time.”
The ZPSD will stay in standby mode if the address does not change between bus cycles
(for example, looping on a single address or a Halt operation). In an alternate system
implementation using an EPROM, SRAM and other discrete components, the system will
consume operating power during the entire bus cycle. This is because the chip select inputs
on the memory devices are usually active throughout the entire cycle. The AC power
consumption of the ZPSD may be calculated using the ALE frequency.
Integrated
Power
Management
Operation
TM
ALE
DISCRETE EPROM, SRAM & LOGIC
ADDRESS
EPROM
ACCESS
SRAM
ACCESS
EPROM
ACCESS
I
CC
ZPSD
ZPSD
ZPSD
TIME
Figure 2. ZPSD Power Operation vs. Discrete Implementation
相關(guān)PDF資料
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