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參數(shù)資料
| 型號： | Z9952AA |
| 英文描述： | SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):15A; Peak Non Repetitive Surge Current, Itsm:225A; Gate Trigger Current Max, Igt:30uA |
| 中文描述： | 11分布式輸出時鐘驅(qū)動器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 46K |
| 代理商： | Z9952AA |
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07085 Rev. *A
06/18/2001
Page 5 of 8
Z9952
Description
The Z9952 has an integrated PLL that provides low skew and low jitter clock outputs for high performance
microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480
MHz. This allows a wide range of output frequencies up to 180MHz. The Z9952 features three banks of individually
configurable outputs: Bank A five outputs, Bank B four outputs, and Bank C two outputs. When MR/OE# input is set
high, all the outputs are tri-stated. The Z9952 outputs are LVCMOS compatible and can drive two series terminated 50
transmission lines. With this capability the Z9952 has an effective fanout of 1:22. Low output-to-output skews make the
Z9952 ideal for clock distribution in nested clock trees in the most demanding of synchronous systems.
The phase detector compares the input reference clock to the external feedback input. For normal operation, the
external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input
reference clock set by SEL(A:C) select inputs, see Table 2. The VCO_SEL input allows for the choice of two VCO
ranges to optimize PLL stability and jitter performance, see Table 1. The VCO frequency is then divided down to provide
the required output frequencies. The use of even dividers ensures that the output duty cycle remains at 50%.
SELA
0
1
QA
÷
4
÷
6
SELB
0
1
QB
÷
4
÷
2
SELC
0
1
QC
÷
2
÷
4
Table 2
Zero Delay Buffer
When used as a zero delay buffer the Z9952 will likely be in a nested clock tree application. Any of the eleven outputs
can be used as the feedback to the PLL. By using one of the outputs as a feedback to the PLL the propagation delay
through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a
near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between
the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the Z9952 is a
function of the configuration used.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z9953 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 180MHz, Multi-Output Zero Delay Buffer |
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| Z9953AA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 180MHz, Multi-Output Zero Delay Buffer |
| Z9960 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer |
| Z9960AL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TWENTY-ONE DISTRIBUTED-OUTPUT CLOCK DRIVER|QFP|48PIN|PLASTIC |
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