參數(shù)資料
型號: Z9952AA
英文描述: SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):15A; Peak Non Repetitive Surge Current, Itsm:225A; Gate Trigger Current Max, Igt:30uA
中文描述: 11分布式輸出時鐘驅(qū)動器
文件頁數(shù): 4/8頁
文件大?。?/td> 46K
代理商: Z9952AA
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07085 Rev. *A
06/18/2001
Page 4 of 8
Z9952
AC Parameters
1
SYMBOL
Freq
Fvco
Tlock
Tr / Tf
Fout
PARAMETER
Reference Input Frequency
PLL VCO Lock Range
Maximum PLL lock Time
Output Clocks Rise / Fall Time
4,5
Maximum Output Frequency
MIN
Note 2
200
TYP
MAX
Note 2
480
10
1.0
180
120
80
TCYCLE/2 +
750
10
8
UNITS
MHz
MHz
ms
ns
MHz
CONDITIONS
0.10
-
0.8V to 2.0V
QB, QC = (
÷
2)
QA, QB, QC = (
÷
4)
QA = (
÷
6)
FoutDC
Output Duty Cycle
4,5
TCYCLE/2 –
750
2
2
ps
tpZL, tpZH
tpLZ, tpHZ
TCCJ
Tpd
TSKEW0
Output enable time (all outputs)
Output disable time (all outputs)
Cycle to Cycle Jitter (peak to peak)
5
REFCLK to FB_IN Delay
3,,4,5
Any Output to Any Output Skew
4,5
ns
ns
ps
ps
ps
+/- 100
-200
-
200
150
250
Same frequencies
Different frequencies
VDDA = VDD = VDDC = 3.3V +/- 5%, TA = -40
°
C to +85
°
C
Note 1:
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with
loaded outputs.
Note 2:
Maximum and minimum input reference is limited by the VCO lock range.
Note 3:
The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the
minimum limits with an increase/decrease of the input reference clock period.
Note 4:
Driving series or parallel terminator 50
(or 50
to VDD/2).
Note 5:
Outputs loaded with 30pF each
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