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參數(shù)資料
| 型號(hào)： | Z9952AA |
| 英文描述： | SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):15A; Peak Non Repetitive Surge Current, Itsm:225A; Gate Trigger Current Max, Igt:30uA |
| 中文描述： | 11分布式輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大小： | 46K |
| 代理商： | Z9952AA |
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07085 Rev. *A
06/18/2001
Page 2 of 8
Z9952
Pin Description
PIN
6
12, 14, 15,
18, 19
22, 23, 26, 27
30, 31
8
1
NAME
PWR
I/O
I
O
Description
REFCLK
QA(0:4)
External Test Clock Input.
Clock Output. See Frequency Table.
VDDC
QB(0:3)
QC(0,1)
FB_IN
VCO_SEL
VDDC
VDDC
O
O
I
Clock Output. See Frequency Table.
Clock Outputs. See Frequency Table.
Feedback Clock Input. Connect to an output for normal operation.
VCO Divider Select Input. When set high, the VCO output is
divided by 2. When set low, the divider is bypassed. See
Table 1
Master Reset/Output Enable Input. When asserted high,
resets all of the internal flip-flops and also disables all of the
outputs. When pulled low, releases the internal flip-flops from
reset and enables all of the outputs.
PLL Enable Input. When asserted low, PLL is enabled. And
when set high, PLL is bypassed.
Frequency Select Inputs. See Frequency Table.
If SEL_ = 0, then QA, QB divider =
÷
4, QC divider =
÷
2
If SEL_ = 1, then QA divider =
÷
6, QB divider =
÷
2, QC divider
=
÷
4
3.3V Power Supply for Output Clock Buffers.
I, PD
5
MR/OE#
I, PD
9
PLL_EN#
I
2, 3, 4
SEL(C:A)
I, PD
16, 20, 21,
25, 32
10
11
7, 13, 17, 24,
28, 29
PD = Internal Pull-Down
VDDC
VDDA
VDD
VSS
3.3V Power Supply for PLL
3.3V Power Supply for Core Logic
Common Ground
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z9953 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 180MHz, Multi-Output Zero Delay Buffer |
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| Z9953AA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 180MHz, Multi-Output Zero Delay Buffer |
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| Z9960AL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TWENTY-ONE DISTRIBUTED-OUTPUT CLOCK DRIVER|QFP|48PIN|PLASTIC |
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