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Z8 Microcontrollers
Interrupts
ZiLOG
UM001600-Z8X0599
7-5
7.4 INTERRUPT INITIALIZATION
After reset, all interrupts are disabled and must be initial-
ized before vectored or polled interrupt processing can be-
gin. The Interrupt Priority Register (IPR), Interrupt Mask
Register (IMR), and Interrupt Request Register (IRQ) must
be initialized, in that order, to start the interrupt process.
7.4.1 Interrupt Priority Register (IPR) Initial-
ization
IPR (Figure 7-7) is a write-only register that sets priorities
for the vectored interrupts in order to resolve simultaneous
interrupt requests. (There are 48 sequence possibilities for
interrupts.) The six interrupt levels IRQ0-IRQ5 are divided
into three groups of two interrupt requests each. One
group contains IRQ3 and IRQ5. The second group con-
tains IRQ0 and IRQ2, while the third group contains IRQ1
and IRQ4.
Priorities can be set both within and between groups as
shown in Tables 7-2 and 7-3. Bits 1, 2, and 5 define the pri-
ority of the individual members within the three groups.
Bits 0, 3, and 4 are encoded to define six priority orders be-
tween the three groups. Bits 6 and 7 are reserved.
Figure 7-7. Interrupt Priority Register
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Interrupt Priority Register (IPR)
Register F9H
Interrupt Group Priority
Bits Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
Group C (IRQ1 and IRQ4 Priority)
1 = IRQ4 > IRQ1
Reserved (Must be 0)
Group B (IRQ0 and IRQ2 Priority)
1 = IRQ0 > IRQ2
Group A (IRQ3 and IRQ5 Priority)
1 = IRQ3 > IRQ5
Table 7-2. Interrupt Priority
Priority
Highest
IRQ1
IRQ4
IRQ2
IRQ0
IRQ5
IRQ3
Group
C
Bit
Bit 1
Value
0
1
0
1
0
1
Lowest
IRQ4
IRQ1
IRQ0
IRQ2
IRQ3
IRQ5
B
Bit 2
A
Bit 5
Table 7-3. Interrupt Group Priority
Bit Pattern
Bit 3
0
0
1
1
0
0
1
1
Group Priority
High
Not Used
C
A
A
B
C
B
Not Used
Bit 4
0
0
0
0
1
1
1
1
Bit 0
0
1
0
1
0
1
0
1
Medium
Low
A
B
C
C
B
A
B
C
B
A
A
C