Z8 Microcontrollers
Instruction Set
ZiLOG
12-10
UM001600-Z8X0599
12.5.1 Op Code Map
10.5
CP
R , R1
2
6.5
DEC
R1
6.5
RLC
R1
6.5
INC
R1
8.0
JP
IRR1
8.5
DA
R1
10.5
POP
R1
6.5
COM
R1
10/12.1
PUSH
R2
6.5
DEC
IR1
6.5
RLC
IR1
6.5
INC
IR1
6.1
SRP
IM
8.5
DA
IR1
10.5
POP
IR1
6.5
COM
IR1
12/14.1
PUSH
IR2
6.5
ADD
r1, r2
6.5
ADC
r1, r2
6.5
SUB
r1, r2
6.5
SBC
r1, r2
6.5
OR
r1, r2
6.5
AND
r1, r2
6.5
TCM
r1, r2
6.5
TM
r1, r2
12.0
LDE
r1, lrr2
12.0
LDE
r2, lrr1
6.5
ADD
r1, Ir2
6.5
ADC
r1, Ir2
6.5
SUB
r1, Ir2
6.5
SBC
r1, Ir2
6.5
OR
r1, Ir2
6.5
AND
r1, Ir2
6.5
TCM
r1, Ir2
6.5
TM
r1, Ir2
18.0
LDEI
lr1, lrr2
18.0
LDEI
lr2, lrr1
10.5
ADD
R2, R1
10.5
ADC
R2, R1
10.5
SUB
R2, R1
10.5
SBC
R2, R1
10.5
OR
R2, R1
10.5
AND
R2, R1
10.5
TCM
R2, R1
10.5
TM
R2, R1
10.5
ADD
IR2, R1
10.5
ADC
IR2, R1
10.5
SUB
IR2, R1
10.5
SBC
IR2, R1
10.5
OR
IR2, R1
10.5
AND
IR2, R1
10.5
TCM
IR2, R1
10.5
TM
IR2, R1
10.5
ADD
R1, IM
10.5
ADC
R1, IM
10.5
SUB
R1, IM
10.5
SBC
R1, IM
10.5
OR
R1, IM
10.5
AND
R1, IM
10.5
TCM
R1, IM
10.5
TM
R1, IM
10.5
ADD
IR1, IM
10.5
ADC
IR1, IM
10.5
SUB
IR1, IM
10.5
SBC
IR1, IM
10.5
OR
IR1, IM
10.5
AND
IR1, IM
10.5
TCM
IR1, IM
10.5
TM
IR1, IM
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Lower Nibble (Hex)
Bytes per Instruction
2
3
2
3
1
10.5
DECW
RR1
6.5
RL
R1
10.5
INCW
RR1
6.5
CLR
R1
6.5
RRC
R1
6.5
SRA
R1
6.5
RR
R1
8.5
SWAP
R1
10.5
DECW
IR1
6.5
RL
IR1
10.5
INCW
IR1
6.5
CLR
IR1
6.5
RRC
IR1
6.5
SRA
IR1
6.5
RR
IR1
8.5
SWAP
IR1
6.5
CP
r1, r2
6.5
XOR
r1, r2
12.0
LDC
r1, Irr2
12.0
LDC
lrr1, r2
6.5
CP
r1, Ir2
6.5
XOR
r1, Ir2
18.0
LDCI
Ir1, Irr2
18.0
LDCI
lrr1, Ir2
10.5
CP
R2, R1
10.5
XOR
R2, R1
10.5
CP
IR2, R1
10.5
XOR
IR2, R1
10.5
CP
R1, IM
10.5
XOR
R1, IM
10.5
CP
IR1, IM
10.5
XOR
IR1, IM
10.5
LD
r1,x,R2
10.5
LD
r2,x,R1
10.5
LD
IR1, IM
20.0
CALL*
IRR1
10.5
LD
R2, R1
20.0
CALL
DA
10.5
LD
R1, IM
6.5
LD
r1, IR2
6.5
LD
Ir1, r2
10.5
LD
IR2, R1
10.5
LD
R2, IR1
6.5
LD
r1, R2
6.5
LD
r2, R1
12/10.5
DJNZ
r1, RA
12/10.0
JR
cc, RA
6.5
LD
r1, IM
12.10.0
JP
cc, DA
6.5
INC
r1
6.0
STOP
7.0
HALT
6.1
DI
6.1
EI
14.0
RET
16.0
IRET
6.5
RCF
6.5
SCF
6.5
CCF
6.0
NOP
4
A
Lower
Op Code
Nibble
Pipeline
Cycles
Mnemonic
Second
Operand
Fetch
Cycles
Upper
Op Code
Nibble
First
Operand
Legend:
R = 8-Bit Address
r = 4-Bit Address
R1 or r1 = Dst Address
R2 or r2 = Src Address
Sequence:
Opcode, First Operand,
Second Operand
Note:
Blank areas are reserved.
*
2-byte instruction appears as
a 3-byte instruction
6.0
WDT
6.0
WDH
U