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Z8 Microcontrollers
Instruction Set
ZiLOG
12-2
UM001600-Z8X0599
12.2 PROCESSOR FLAGS
The Flag Register (FCH) informs the user of the current
status of the Z8. The flags and their bit positions in the Flag
Register are shown in Figure 12-1.
The Z8 Flag Register contains six bits of status information
which are set or cleared by CPU operations. Four of the
bits (C, V, Z and S) can be tested for use with conditional
Jump instructions. Two flags (H and D) cannot be tested
and are used for BCD arithmetic. The two remaining bits in
the Flag Register (F1 and F2) are available to the user, but
they must be set or cleared by instructions and are not us-
able with conditional Jumps.
As with bits in the other control registers, the Flag Register
bits can be set or reset by instructions; however, only
those instructions that do not affect the flags as an out-
come of the execution should be used (Load Immediate).
Note:
The Watch-Dog Timer (WDT) instruction effects
the Flags accordingly: Z=1, S=0, V=0.
Table 12-5. Bit Manipulation Instructions
Mnemonic
TCM
Operands
dst, src
Instruction
Test Complement
Under Mask
Test Under Mask
Bit Clear
Bit Set
Bit Complement
TM
AND
OR
XOR
dst, src
dst, src
dst, src
dst, src
Table 12-6. Block Transfer Instructions
Mnemonic
LDCI
Operands
dst, src
Instruction
Load Constant
Auto Increment
Load External
Auto Increment
LDEI
dst, src
Table 12-7. Rotate and Shift Instructions
Mnemoni
c
RL
RLC
RR
RRC
SRA
SWAP
Operands
dst
dst
dst
dst
dst
dst
Instruction
Rotate Left
Rotate Left Through Carry
Rotate Right
Rotate Right Through Carry
Shift Right Arithmetic
Swap Nibbles
Table 12-8. CPU Control Instructions
Mnemoni
c
CCF
DI
EI
HALT
NOP
RCF
SCF
SRP
STOP
WDH
WDT
Operands
Instruction
Complement Carry Flag
Disable Interrupts
Enable Interrupts
Halt
No Operation
Reset Carry Flag
Set Carry Flag
Set Register Pointer
Stop
WDT Enable During HALT
WDT Enable or Refresh
src