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XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
63
TABLE 40: MICROPROCESSOR REGISTER 0X0FH BIT DESCRIPTION
CHANNEL 0-13 (0X0FH-0XDFH)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
0
D[6:0]
8SEG[6:0]
Segment Number Eight, Same Description as Register 0x08h
R/W
TABLE 41: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION
GLOBAL REGISTER (0XE0H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
SR/DR
Single Rail/Dual Rail Mode
This bit sets the LIU to receive and transmit digital data in a single
rail or a dual rail format.
0 = Dual Rail Mode
1 = Single Rail Mode
R/W
0
D6
ATAOS
Automatic Transmit All Ones
If ATAOS is selected, an all ones pattern will be transmitted on any
channel that experiences an RLOS condition. If an RLOS condi-
tion does not occur, TAOS will remain inactive.
0 = Disabled
1 = Enabled
R/W
0
D5
RCLKE
Receive Clock Data
0 = RPOS/RNEG data is updated on the rising edge of RCLK
1 = RPOS/RNEG data is updated on the falling edge of RCLK
R/W
0
D4
TCLKE
Transmit Clock Data
0 = TPOS/TNEG data is sampled on the falling edge of TCLK
1 = TPOS/TNEG data is sampled on the rising edge of TCLK
R/W
0
D3
DATAP
Data Polarity
0 = Transmit input and receive output data is active "High"
1 = Transmit input and receive output data is active "Low"
R/W
0
D2
Reserved
This Register Bit is Not Used
R/W
0