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參數資料
| 型號： | XR17V354IB-0A-EVB |
| 廠商： | Exar Corporation |
| 文件頁數： | 39/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR17V354-A 176BGA |
| 產品培訓模塊： | PCIe UARTs |
| 標準包裝： | 1 |
| 主要目的： | 接口，UART |
| 嵌入式： | 否 |
| 已用 IC / 零件： | XR17V354 |
| 已供物品： | 板 |
| 其它名稱： | 1016-1611 XR17V354IB-0A-EVB-ND |
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XR17V354
44
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.3
3.7
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X, 8X or 4X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X, 8X or 4X clock rate. After 8 or 4 or 2 clocks the start bit period should be at the center of
the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits [4:1]. Upon unloading the receive data byte from RHR, the receive FIFO
pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in RHR
register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches
the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out
function when receive data does not reach the receive FIFO trigger level. This time-out delay is 4 word lengths
as defined by LCR bits [1:0] plus 12 bits time. The RHR interrupt is enabled by IER bit [0].
3.7.1
Receiver Operation in non-FIFO Mode
FIGURE 15. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
16X or 8X or 4X
Clock
Receive Data Characters
Data Bit
Validation
Error
Flags in
LSR bits
4:2
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XR17V354IB176-F | 功能描述:UART 接口集成電路 4 Channel PCIe UART w/256 Byte FIFO RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17V354IB-E4-EVB | 功能描述:界面開發(fā)工具 Eval Board for XR17V354IB-E4 RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR17V354IB-E8-EVB | 功能描述:界面開發(fā)工具 Eval Board for XR17V354IB-E8 RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR17V358 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE OCTAL PCI EXPRESS UART |
| XR17V358IB-0A-EVB | 功能描述:界面開發(fā)工具 Eval Board for XR17V358IB-0A RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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