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參數(shù)資料
| 型號(hào)： | XR17L154CV |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 9/58頁 |
| 文件大小： | 676K |
| 代理商： | XR17L154CV |
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XR17L154
3.3V PCI BUS QUAD UART
REV. 1.0.0
á
9
1.2
The device configuration registers and a special way to access each of the UART’s transmit and receive data
FIFOs are accessible directly from the PCI data bus. This provides easy programming of general operating
parameters to the L154 UART and for monitoring the status of various functions. The registers occupy 2K of
PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded
into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. These registers
control or report on all 4 channel UARTs functions that include interrupt control and status, 16-bit general
purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft-
reset control, and device identification and revision, and others.
The registers set is mapped into 4 address blocks where each UART channel occupies 512 bytes memory
space for its own 16550 compatible configuration registers. The device configuration and control registers are
embedded inside the UART channel zero’s address space between 0x0080 to 0x0093. All these registers can
be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host at beginning of the
bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register’s
address. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer
is automatically bumped to the next sequential data location either in byte, word or dword. One special case
applies to the receive data unloading when reading the receive data together with its LSR register content. The
host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated
error flags.
Device configuration Register Set
15:0
RWR
1
Subsystem Vendor ID (write
from external EEPROM by cus-
tomer)
0x0000
0x30
31:0
RO
Expansion ROM Base Address (Unimplemented)
0x00000000
0x34
31:0
RO
Reserved (returns zeros)
0x00000000
0x38
31:0
RO
Reserved (returns zeros)
0x00000000
0x3C
31:24
RO
Unimplemented MAXLAT
0x00
23:16
RO
Unimplemented MINGNT
0x00
15:8
RO
Interrupt Pin, use INTA#.
0x01
7:0
RWR
Interrupt Line.
0xXX
N
OTE
:
RWR
1
=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. WO=Write Only.
T
ABLE
1: PCI L
OCAL
B
US
C
ONFIGURATION
S
PACE
R
EGISTERS
A
DDRESS
B
ITS
T
YPE
D
ESCRIPTION
R
ESET
V
ALUE
(
HEX
)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR17L154IV | Telecomm/Datacomm |
| XR-2011CN | Septuple Peripheral Driver |
| XR-2012CN | Septuple Peripheral Driver |
| XR-2013CN | Septuple Peripheral Driver |
| XR-2014CN | Septuple Peripheral Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17L154IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS QUAD UART |
| XR17V252 | 制造商:EXAR 制造商全稱:EXAR 功能描述:66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT |
| XR17V252_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT |
| XR17V252IM | 功能描述:UART 接口集成電路 66MHz Dual PCI UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17V252IM-0A-EVB | 功能描述:UART 接口集成電路 Supports V252 100 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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