參數(shù)資料
型號: XR17L154CV
元件分類: 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述: Telecomm/Datacomm
中文描述: 電信/數(shù)據(jù)通信
文件頁數(shù): 17/58頁
文件大小: 676K
代理商: XR17L154CV
XR17L154
3.3V PCI BUS QUAD UART
REV. 1.0.0
á
17
1.2.9
The L154 provides 8 multi-purpose inputs/outputs [MPIO7:0] for general use. Each pin can be programmed to
be an input or output function. The input logic state can be set for normal or inverted level, and optionally set to
generate an interrupt. The outputs can be set to be normal logic 1 or 0 state, or tri-state. Their functions and
definitions are programmed through 5 registers: MPIOINT, MPIOLVL, MPIO3T, MPIOINV and MPIOSEL. If all 8
pins are set for inputs, all 8 interrupts would be or’ed together. The Or’ed interrupt is reported in the channel 0
UART interrupt status, see Interrupt Status Register. The pins may also be programmed to be outputs and to
the tri-state condition for signal sharing.
1.2.10
MPIO REGISTER
Bit 7 represents MPIO7 pin and bit 0 represents MPIO0 pin. There are 5 registers that select, control and
monitor the 8 multipurpose inputs and outputs pins.
Figure 6
shows the internal circuitry.
Multi-Purpose Inputs and Outputs
F
IGURE
6. M
ULTIPURPOSE
INPUT
/
OUTPUT
INTERNAL
CIRCUIT
MPIO
Pin [7:0]
MPIOLVL [7:0]
Read Input Level
MPIOINT [7:0]
Rising Edge
Detection
INT
OR
AND
AND
1
0
MPIOSEL [7:0]
(Select Input=1, Output=0 )
MPIO3T [7:0]
(3-state Enable =1)
MPIOLVL [7:0]
(Output Level)
MPIOINV [7:0]
(Input Inversion Enable =1)
MPIOCKT
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