參數(shù)資料
型號(hào): XR17L154CV
元件分類: 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具
英文描述: Telecomm/Datacomm
中文描述: 電信/數(shù)據(jù)通信
文件頁(yè)數(shù): 13/58頁(yè)
文件大?。?/td> 676K
代理商: XR17L154CV
XR17L154
3.3V PCI BUS QUAD UART
REV. 1.0.0
á
13
Registers INT3, INT2 and INT1 [32:8]
Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit,
and status. Bit [10:8] represent channel 0 and go up to channel 3 with bits [19:17]. The 3 bit encoding and their
priority order are shown below in
Table 5
. The Timer and MPIO interrupts are for the device and therefore they
exist within channel 0 space and not in other channel interrupt.
.
F
IGURE
4. T
HE
G
LOBAL
I
NTERRUPT
R
EGISTER
, INT0, INT1, INT2
AND
INT3
T
ABLE
5: UART C
HANNEL
[3:0] I
NTERRUPT
S
OURCE
E
NCODING
P
RIORITY
B
IT
[
N
+2]
B
IT
[
N
+1]
B
IT
[
N
]
I
NTERRUPT
S
OURCE
(
S
)
x
0
0
0
None
1
0
0
1
RXRDY and RX Line Status (logic OR of LSR[4:1])
2
0
1
0
RXRDY Time-out
3
0
1
1
TXRDY, THR or TSR (auto RS485 mode) empty
4
1
0
0
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
5
1
0
1
Reserved.
6
1
1
0
MPIO pin(s). Available only within channel 0, reserved in other channels.
7
1
1
1
TIMER Time-out. Available only within channel 0, reserved in other channels.
Channel-3
Channel-2
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
INT0 Register
Rsvd
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Ch-3
Ch-2
Ch-1
Ch-0
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Rsvd
Rsvd Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
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