REV. 1.2.2 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 17 2.2.2 General Purpose 16-bit Timer/Counter [TIMERMSB, TIME" />
參數(shù)資料
型號: XR17D154CV
廠商: Exar Corporation
文件頁數(shù): 9/69頁
文件大?。?/td> 0K
描述: IC UART PCI BUS QUAD 144LQFP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝: 60
特點: *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
xr
XR17D154
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
17
2.2.2
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT
0XXX-XX-00-00)
A 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal
crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or
re-triggerable for continue interval. An interrupt may be generated in the INT Register when the timer times out.
It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These
registers provide start/stop and re-triggerable or one-shot operation. The time-out output of the Timer can be
set to generate an interrupt for system or event alarm.
TABLE 7: UART CHANNEL [3:0] INTERRUPT CLEARING:
RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level.
RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon interrupt clears after reading the ISR register that is in the UART channel register set.
Special character detect interrupt is cleared by a read to ISR or after the next character is received.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
FIGURE 7. TIMER/COUNTER CIRCUIT.
TABLE 8: TIMER CONTROL REGISTERS
TIMERCNTL [0]
Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
TIMERCNLT [1]
Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
TIMERCNTL [2]
Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function.
TIMERCNTL [3]
Logic zero (default) selects internal and logic one selects external clock to the timer/counter.
TIMERCNTL [4]
Routes the Timer-Counter interrupt to MPIO[0] if MPIOSEL[0]=0 for external event control.
TIMERCNTL [7:5] Reserved (defaults to zero)
TMRCK
OSC. CLOCK
TIMERCNTL [3]
16-Bit
Timer/Counter
TIMERCNTL [2]
Re-trigger
Single-shot
TIMERCNTL [1]
Start/Stop
TIMERCNTL [0]
Timer Interrupt, Ch-0 INT=7
Time-out
Timer Interrupt Enable
Single/Re-triggerable
TIMERMSB and TIMERLSB
(16-bit Value)
0
1
0
1
0
1
No Interrupt
Clock
Select
TIMERCNTL [4]
0
1
MPIO[0]
MPIOLVL[0]
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