REV. 1.2.2 30 5.3 Receiver The receiver section contains an 8-bit Receive S" />
參數(shù)資料
型號: XR17D154CV
廠商: Exar Corporation
文件頁數(shù): 24/69頁
文件大?。?/td> 0K
描述: IC UART PCI BUS QUAD 144LQFP
產品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標準包裝: 60
特點: *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設備封裝: 144-LQFP(20x20)
包裝: 托盤
XR17D154
xr
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. 1.2.2
30
5.3
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start
bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 1- 4 and an LSR interrupt is generated immediately if IER bit-2 is enabled.
Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach
the receive FIFO trigger level. This time-out delay is 4 word lengths as defined by LCR[1:0] plus 12 bits time.
The RHR interrupt is enabled by IER bit-0.
5.3.1
Receive Holding Register (RHR) - Read-Only
The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register
(RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this
register whenever a data byte is transferred from the RSR. RHR also part of the receive FIFO of 64 bytes by
11-bit wide, 4 extra bits are for the error tags to be in LSR register. When the FIFO is enabled by FCR bit-0, it
acts as the first-out register of the FIFO as new data are put over the first-in register. The receive FIFO pointer
is bumped after the RHR register is read. Also, the error tags associated with the data byte are immediately
updated onto the line status register (LSR) bits 1-4.
5.3.2
Receiver Operation in non-FIFO Mode
FIGURE 14. RECEIVER OPERATION IN NON-FIFO MODE
R e c e iv e D a ta S h ift
Re g is te r ( R SR)
Re c e iv e
D a ta B y te
a n d E rro rs
R H R In te rru p t (IS R b it-2 )
Re c e iv e D a ta
Ho ld in g Re g is te r
( R HR)
RX F IF O
16X o r 8 X C loc k
( 8 X M O D E R egister )
R e c e iv e D a ta C har ac te r s
Da ta Bit
Va lid a tio n
E rro r
F lags in
LS R bits
4:1
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