![](http://datasheet.mmic.net.cn/Exar-Corporation/XR17D154CV-F_datasheet_100069/XR17D154CV-F_56.png)
XR17D154
xr
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. 1.2.2
56
AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 3.0-5.5V)
TA=0o to 70oC (-40o to +85oC for industrial grade package).
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
XTAL1
UART Crystal Oscillator
24
MHz
On-chip osc.
ECLK
External Clock
33
MHz
VCC = 3.3V ±10%
50
MHz
VCC = 5V ±10%
TECLK
External Clock Period
(TECLK = 1/ECLK)
30
ns
VCC = 3.3V ±10%
20
ns
VCC = 5V ±10%
TECH, TECL External Clock High/Low
Time
13
ns
VCC = 3.3V ±10%
8
ns
VCC = 5V ±10%
IOH(AC)
Switching Current High
-12VIO
mA
See PCI Specification
Rev. 2.3
IOL(AC)
Switching Current Low
16VIO
mA
See PCI Specification
Rev. 2.3
ICH
High Clamp Current
25+(Vin-VIO-1)/0.015
mA
VIO+4 > Vin
≥ VIO+1
ICL
Low Clamp Current
-25+(Vin+1)/0.015
mA
-3 < Vin
≤ -1
SlewR
Output Rise Slew Rate
1
4
V/ns
0.2VIO - 0.6VIO load
SlewF
Output Fall Slew Rate
1
4
V/ns
0.6VIO - 0.2VIO load
TCYC
CLK Cycle Time
30
∞
ns
PCI Bus Clock, CLK
THI
CLK High Time
11
ns
TLO
CLK Low Time
11
ns
CLK Slew Rate
1
4
V/ns
TVAL
CLK to Signal Valid Delay
2
11
ns
TON
Float to Active Delay
2
ns
TOFF
Active to Float Delay
28
ns
TSETUP
Input Setup Time to CLK -
bused signals
7
ns
THOLD
Input Hold Time from CLK
0
ns
TPRST
RST# Active Time After
Power Stable
1
ms
TCRST#
RST# Active Time After CLK
Stable
100
us
RST# Slew Rate
50
mV/ns