REV. 1.2.2 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 29 5.2.3 Transmitter Operation in FIFO mode The host may fill the transmit FIF" />
參數資料
型號: XR17D154CV
廠商: Exar Corporation
文件頁數: 22/69頁
文件大?。?/td> 0K
描述: IC UART PCI BUS QUAD 144LQFP
產品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標準包裝: 60
特點: *
通道數: 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設備封裝: 144-LQFP(20x20)
包裝: 托盤
xr
XR17D154
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
29
5.2.3
Transmitter Operation in FIFO mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty
interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit-5=1) the source of the transmit
empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not
changed until the last stop bit of the last character is shifted out.
5.2.4
Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit-5. While transmitting, the RTS# or DTR# signal is HIGH. The RTS# or DTR# signal changes from HIGH to
LOW after a specified delay indicated in MSR[7:4] following the last stop bit of the last character that has been
transmitted. This helps in turning around the transceiver to receive the remote station’s response. The delay
optimizes the time needed for the last transmission to reach the farthest station on a long cable network before
switching off the line driver. This delay prevents undesirable line signal disturbance that causes signal
degradation. It also changes the transmitter empty interrupt to TSR empty instead of THR empty.
FIGURE 12. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 13. TRANSMIITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X or 8X
Clock
(8XMODE
Register)
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below Programmed Trigger
Level (TXTRG) and then
when becomes empty. FIFO
is Enabled by FCR bit-0=1
Transmit
FIFO
(64-Byte)
TXFIFO1
16X or 8X Clock
(8XMODE Register)
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
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