REV. 1.2.2 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 21 2.2.10 MPIO REGISTER Bit 7 represents MPIO7 pin and bit 0 represents MPIO0 " />
參數(shù)資料
型號(hào): XR17D154CV-0A-EVB
廠商: Exar Corporation
文件頁(yè)數(shù): 14/69頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17D154 144TQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
xr
XR17D154
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
21
2.2.10
MPIO REGISTER
Bit 7 represents MPIO7 pin and bit 0 represents MPIO0 pin. There are 5 registers that select, control and
monitor the 8 multipurpose inputs and outputs pins. Figure 8 shows the internal circuitry.
MPIOINT [7:0] - (default 0x00)
Enable multipurpose input pin interrupt. If the pin is selected by MPIOSEL as input then bit-0 enables input pin
0 for interrupt, and bit-7 enables input pin 7. No interrupt is enable if the pin is selected to be an output. The
interrupt is edge sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears after
a read to register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being active
low or active high, it’s level trigger. Logic 0 (default) disables the pin’s interrupt and logic 1 enables it.
FIGURE 8. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT
MPIO
Pin [7:0]
MPIOLVL [7:0]
Read Input Level
MPIOINT [7:0]
Rising Edge
Detection
INT
OR
AND
1
0
MPIOSEL [7:0]
(Select Input=1, Output=0 )
MPIO3T [7:0]
(3-state Enable =1)
MPIOLVL [7:0]
(Output Level)
MPIOINV [7:0]
(Input Inversion Enable =1)
MPIOCKT
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOINT Register
Multipurpose Input/Output Interrupt Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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