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XR17D152
á
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
REV. 1.2.0
12
TABLE 2: XR17D152 DEVICE CONFIGURATION REGISTERS
OFFSET ADDRESS
MEMORY SPACE
READ/WRITE
DATA WIDTH
COMMENT
0x000 - 0x00F
UART channel 0 Regs
8/16/24/32
First 8 regs are 16550 compatible
0x010 - 0x07F
Reserved
0x080 - 0x093
DEVICE CONFIG.
REGISTERS
8/16/24/32
0x094 - 0x0FF
Reserved
Read/Write
0x100 - 0x13F
UART 0 – Read FIFO
Read-Only
8/16/24/32
64 bytes of RX FIFO data
0x100 - 0x13F
UART 0 – Write FIFO
Write-Only
8/16/24/32
64 bytes of TX FIFO data
0x140 - 0x17F
Reserved
0x180 - 0x1FF
UART 0 – Read FIFO
with status
Read-Only
16/32
64 bytes of RX FIFO data + 64 bytes
of LSR status information
0x200 - 0x20F
UART channel 1 Regs
8/16/24/32
First 8 regs are 16550 compatible
0x210 - 0x2FF
Reserved
Read/Write
0x300 - 0x33F
UART 1 – Read FIFO
Read-Only
8/16/24/32
64 bytes of RX FIFO data
0x300 - 0x33F
UART 1 – Write FIFO
Write-Only
8/16/24/32
64 bytes of TX FIFO data
0x340 - 0x37F
Reserved
0x380 - 0x3FF
UART 1 – Read FIFO
with status
Read-Only
16/32
64 bytes of RX FIFO data + 64 bytes
of LSR status information
TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT
ADDRESS
[A7:A0]
REGISTER
READ/WRITE COMMENT
RESET STATE
Ox080
INT0 [7:0]
Read-only Interrupt [1:0], Reserved [7:2]
Bits 7-0 = 0x00
Ox081
INT1 [15:8]
Read-only [5:0], Reserved [7:6]
Bits 7-0 = 0x00
Ox082
INT2 [23:16]
Reserved
Bits 7-0 = 0x00
Ox083
INT3 [31:24]
Reserved
Bits 7-0 = 0x00
Ox084
TIMERCNTL
Read/Write Timer Control
Bits 7-0 = 0x00
Ox085
TIMER
Reserved
Bits 7-0 = 0x00
Ox086
TIMERLSB
Read/Write Timer LSB
Bits 7-0 = 0x00
Ox087
TIMERMSB
Read/Write Timer MSB
Bits 7-0 = 0x00
Ox088
8XMODE
Read/Write [1:0], Reserved [7:2]
Bits 7-0 = 0x00
Ox089
REGA
Reserved
Bits 7-0 = 0x00