- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1975 > XR17D152CM-F (Exar Corporation)IC UART PCI BUS DUAL 100TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XR17D152CM-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 21/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UART PCI BUS DUAL 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | UART Product Overview |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 3.3V，5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1288 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)
XR17D152
á
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
REV. 1.2.0
28
5.3
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start
bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR bits 1-4 and an LSR interrupt is generated immediately if IER bit-2 is enabled. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the LSR bits are
immediately updated to reflect the status of the data byte in the RHR. The RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach
the receive FIFO trigger level. This time-out delay is 4 word lengths as defined by LCR[1:0] plus 12 bits time.
The RHR interrupt is enabled by IER bit-0.
5.3.1
Receive Holding Register (RHR)
The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register
(RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this
register whenever a data byte is transferred from the RSR. The RHR is also part of the receive FIFO of 64
bytes by 11-bit wide, 3 extra bits are for the error tags in LSR. When the FIFO is enabled by FCR bit-0, the
RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is
loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR
bits 1-4.
FIGURE 13. TRANSMIITTER OPERATION IN FIFO AND FLOW CONTROL MODE
T ra n sm it D a ta S h ift R e g iste r
(T S R )
Tra n sm it
D a ta B y te
T H R In te rru p t (IS R b it-1 ) fa lls
be lo w P rogram m e d T rigger
Le v e l (T X T R G ) and then
w hen b e co m e s em p ty. F IF O
is E nab le d by F C R b it-0=1
Tra n sm it
FIF O
(64-B yte )
TX F IFO 1
16 X or 8X C lock
(8 X M O D E R egister)
A u to C T S F low C o ntro l (C T S # pin)
Au to So ftw a re F lo w C o n tro l
F lo w C ontro l C haracte rs
(X off1 /2 an d X o n 1 /2 R eg.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR17D154CV-F | IC UART PCI BUS QUAD 144LQFP |
| XR17D158IV-F | IC UART PCI BUS OCTAL 144LQFP |
| XR17V252IM | IC UART PCI BUS DUAL 100TQFP |
| XR17V254IV-F | IC UART PCI BUS QUAD 144LQFP |
| XR17V258IV-F | IC UART PCI BUS OCTAL 144LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17D152CMTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17D152IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART |
| XR17D152IM-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17D154 | 制造商:EXAR 制造商全稱:EXAR 功能描述:UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART |
| XR17D154CV | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。